From patchwork Sun Dec 12 18:19:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Perier X-Patchwork-Id: 12695806 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 45400C433EF for ; Sun, 12 Dec 2021 18:21:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=rwPsmxop9t4qQYJrfwIOXcEwef5CSACCguk08XrvuQ4=; b=oQxbEXWuCPYRJw 44OaPqC4CXteb0t+Bv5zK8RFiq26xGTyyTHpsHZaVFMGkl+yKUkolbye0Foti2JLlkfhrq0ut5OGv nR+YiePDvnSx8xyGjk7lIxhUcCQ2I+9dFPMuSSiRr8cAxAVtmlT0LNriWtpMZlAx0X8UkOQWW4neC +1JUGjGjHkgc5Qp6qzDd7DbJFMo4Xr1w7BxJ13M5XCFfm6gEv8OuzO0nDDU5tLOxkqpbteOr8KwPL 6qlueecJZgBKQGxp4miDKb3i30U5Y52FarebRUXbXE2fkSWsrY2gwr4owfMj5A+5JFqOzCqeyBsFM dyA0A1w0D72w8SaBl3cA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mwTRg-006vfb-2G; Sun, 12 Dec 2021 18:19:36 +0000 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mwTRJ-006vW1-9t for linux-arm-kernel@lists.infradead.org; Sun, 12 Dec 2021 18:19:14 +0000 Received: by mail-wr1-x42f.google.com with SMTP id v11so23518560wrw.10 for ; Sun, 12 Dec 2021 10:19:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=s89O9UyBnTEz8pj2LKhsXhinnDR/gR0LdEysrofCZnU=; b=W09La0BG+7pSgIm8pns3h5Skv/cgZCnaGCsZx3T32PGEMSnINojslOO4WUORoM0nh2 BFcfEAAuXYaBKckeiXHLVO5vrbjIqmiG81nYvey0eFnL9MvJGcZIYP5Rk44U4QeusBx7 3BUZp/PAtVdGLrhi94MaEephWMuI/WvoruuBP9PO32wCfR74zlAPa5gH4AwKEmnbxwN3 rKisWfqrclLAHGvJhgm62YYZriUkR2Tk0sWtLgBQv+nxVbE2IrjQ1OyiZlkQCov1rOSg 6btGMIi90+q3qwkWHNfSBob6k4HiQl75mOfNegfMTpYmEiRkNoDAmcMqvDS7BsPWgOnA mEIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=s89O9UyBnTEz8pj2LKhsXhinnDR/gR0LdEysrofCZnU=; b=ZtCiSbWfVasQB+D6mRkSmgmI2aX7+SmBwut6cAHvB4qJM43MQ7nonT3VSBXopYQkst irXkOo0pa8Rv3zTlhxT+EcxC9RCH91Waykum3stZJFuupLyHtF8vBIawonzTkCUV6SP5 HS07Xz7/hwZvO8R5uFGNPvtLA+X1B6gvVyB2SNw/FCd26CqUMJTX6o2xdBgy7ui2NWlQ JQUiNl1a8GwGBwNzu3HNXzq/gaNGRHvjhRdDrgbRJpkld44OBSkY1S8dtqnzPkGCmoIf 04K3NZo0kEWqnZ6e8y5mbyOO7n3ak+KKcrhko8fEA9Xy+bo04ci+PmJw38eqmCpPGo20 fTLA== X-Gm-Message-State: AOAM533836rxQdi64/E1gvxkZWPhJdK6PufREwThih7w5bDVouQcFJQi USd1BgpoMt0h3bio/NPfbe/yh0857dQ= X-Google-Smtp-Source: ABdhPJxw0+E/eGq5Uq2YIXWQ7Qq4DjXeY7Pi14KDR0/z1eOqy92l3jQg8gIKZFhe3LgUpWZX+b5yNw== X-Received: by 2002:a5d:58f9:: with SMTP id f25mr26777535wrd.206.1639333151056; Sun, 12 Dec 2021 10:19:11 -0800 (PST) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id l4sm8263879wrv.94.2021.12.12.10.19.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Dec 2021 10:19:10 -0800 (PST) From: Romain Perier To: Daniel Lezcano , Thomas Gleixner , Daniel Palmer , Romain Perier , Rob Herring , Russell King Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/6] clocksource: msc313e: Add support for ssd20xd-based platforms Date: Sun, 12 Dec 2021 19:19:02 +0100 Message-Id: <20211212181906.94062-3-romain.perier@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211212181906.94062-1-romain.perier@gmail.com> References: <20211212181906.94062-1-romain.perier@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211212_101913_365250_5EA185FB X-CRM114-Status: GOOD ( 13.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org SSD20X family SoCs have an oscillator running at ~432Mhz for timer1 and timer2, while timer0 is running at 12Mhz. There are no ways to reduce or divide these clocks in the clktree. However, SSD20X SoCs provide an internal "timer_divide" register that can act on this input oscillator. This commit adds support for this register, as timer1 and timer2 are used as clockevents these will run at 48Mhz. Signed-off-by: Romain Perier --- drivers/clocksource/timer-msc313e.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clocksource/timer-msc313e.c b/drivers/clocksource/timer-msc313e.c index 154e73444a0c..54c54ca7c786 100644 --- a/drivers/clocksource/timer-msc313e.c +++ b/drivers/clocksource/timer-msc313e.c @@ -33,7 +33,9 @@ #define MSC313E_REG_TIMER_MAX_HIGH 0x0c #define MSC313E_REG_COUNTER_LOW 0x10 #define MSC313E_REG_COUNTER_HIGH 0x14 +#define MSC313E_REG_TIMER_DIVIDE 0x18 +#define MSC313E_CLK_DIVIDER 9 #define TIMER_SYNC_TICKS 3 #ifdef CONFIG_ARM @@ -179,6 +181,12 @@ static int __init msc313e_clkevt_init(struct device_node *np) if (ret) return ret; + if (of_device_is_compatible(np, "sstar,ssd20xd-timer")) { + to->of_clk.rate = clk_get_rate(to->of_clk.clk) / MSC313E_CLK_DIVIDER; + to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ); + writew(MSC313E_CLK_DIVIDER - 1, timer_of_base(to) + MSC313E_REG_TIMER_DIVIDE); + } + msc313e_clkevt.cpumask = cpu_possible_mask; msc313e_clkevt.irq = to->of_irq.irq; to->clkevt = msc313e_clkevt; @@ -242,3 +250,4 @@ static int __init msc313e_timer_init(struct device_node *np) } TIMER_OF_DECLARE(msc313, "mstar,msc313e-timer", msc313e_timer_init); +TIMER_OF_DECLARE(ssd20xd, "sstar,ssd20xd-timer", msc313e_timer_init);