From patchwork Sat Dec 18 20:00:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Schleich X-Patchwork-Id: 12696774 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3B017C433F5 for ; Sat, 18 Dec 2021 20:13:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date:Subject:Cc:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=PGmZOLaWO4+PAcarcQY0sKejnPcfchtHMe9oobOpCFQ=; b=jKssuhzcxkmlb5 fDP9i7zD0w3wJ4V0DMtNFnKDAv6PYUw8f4EjzXT1oMEC46rPvOyqYo2kqZCeyUmKz+x4hfnKCXuJ5 RB9WQLRAcAkkf4GLMzbcnVqkpk1csLKXfzhx3wu46YIIL6FffddxjR21DPGSmLC8lJ0E6KtJtrCba MzS/WuI4rSftfAy6wTXmeJIWWolBiWBSuZ59jFllei7Uwh+Ijn0gDm5ajKgIMTyiOcx4y+DjTwecP kkzPYJXvHwKNx3A80B2BITf3xS13In26gvRU58YS5rTAUxvuCIrx5bpBP5li4s89plr5FUeXzMPpD P7CCZq7Ennvu1zt82OxQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1myg3q-00Edc1-RC; Sat, 18 Dec 2021 20:12:06 +0000 Received: from mail.noreya.tech ([46.38.236.86]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1myg3n-00EdbV-Kt for linux-arm-kernel@lists.infradead.org; Sat, 18 Dec 2021 20:12:05 +0000 Received: from localhost (localhost [127.0.0.1]) by mail.noreya.tech (Postfix) with ESMTP id 16BA7392; Sat, 18 Dec 2021 21:04:08 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=noreya.tech; s=s2048; t=1639857848; bh=fLvKvgtjY8Q8G/HKVKFbFawJR1AzhXvOwLc2pAeiOuA=; h=From:To:Cc:Subject:Date:From; b=L3rkgg9ypEvwaG/VYCXmh0psfkdus+fcoltfKDoYigmpaeKRi6kQ13wGspfLLsBv2 mbUGOHdd6xQNLVnU2xcYOFB9t+WZpegtdFflbn97Zfvu5FLXcUY9NsWHjQ+gQFUofd DtwPwUkT0Mh9J2+2fBibkO2yD6wMty+0ALclYY+fQMD8ihkUoYgLB1a/3aX8aXfAAe 1hDf8WtqvetXavGRctCq4siB+gaKHky0MU0qDa/jEL2TBD8MH7jacYeYroZlT/hyPo VCq85Q/0Zd4LmdA0VxGjoiEOZzguYwTp8riMFRn9Frz9gt6pxR86k/m4tbMKC2cXEi vFMVViHL/GJTg== X-Virus-Scanned: Debian amavisd-new at mail.noreya.tech Received: from mail.noreya.tech ([127.0.0.1]) by localhost (mail.noreya.tech [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id 5vBD5DB9ThRR; Sat, 18 Dec 2021 21:04:05 +0100 (CET) Received: from richard-AX370.lan (17-12-121.cgnat.fonira.net [185.17.12.121]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mail.noreya.tech (Postfix) with ESMTPSA; Sat, 18 Dec 2021 21:04:05 +0100 (CET) From: Richard Schleich To: robh+dt@kernel.org, nsaenz@kernel.org, f.fainelli@gmail.com, bcm-kernel-feedback-list@broadcom.com, devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org Cc: Richard Schleich Subject: [PATCH] ARM: dts: bcm2837: Add the missing L1/L2 cache information Date: Sat, 18 Dec 2021 21:00:09 +0100 Message-Id: <20211218200009.16856-1-rs@noreya.tech> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211218_121203_995352_5AFADB38 X-CRM114-Status: GOOD ( 11.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch fixes the kernel warning "cacheinfo: Unable to detect cache hierarchy for CPU 0" for the bcm2837 on newer kernel versions. Signed-off-by: Richard Schleich Tested-by: Stefan Wahren --- arch/arm/boot/dts/bcm2837.dtsi | 49 ++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi index 0199ec98cd61..1af1616982bb 100644 --- a/arch/arm/boot/dts/bcm2837.dtsi +++ b/arch/arm/boot/dts/bcm2837.dtsi @@ -40,12 +40,26 @@ #size-cells = <0>; enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit + /* Source for d/i-cache-line-size and d/i-cache-sets + * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system + * /about-the-l1-memory-system?lang=en + * + * Source for d/i-cache-size + * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks + */ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x000000d8>; + d-cache-size = <0x8000>; // 32KiB + d-cache-line-size = <64>;// Data side cache line length of 64 bytes + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; // 32KiB + i-cache-line-size = <64>;// Instruction side cache line length of 64 bytes + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + next-level-cache = <&l2>; }; cpu1: cpu@1 { @@ -54,6 +68,13 @@ reg = <1>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x000000e0>; + d-cache-size = <0x8000>; // 32KiB + d-cache-line-size = <64>;// Data side cache line length of 64 bytes + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; // 32KiB + i-cache-line-size = <64>;// Instruction side cache line length of 64 bytes + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + next-level-cache = <&l2>; }; cpu2: cpu@2 { @@ -62,6 +83,13 @@ reg = <2>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x000000e8>; + d-cache-size = <0x8000>; // 32KiB + d-cache-line-size = <64>;// Data side cache line length of 64 bytes + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; // 32KiB + i-cache-line-size = <64>;// Instruction side cache line length of 64 bytes + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + next-level-cache = <&l2>; }; cpu3: cpu@3 { @@ -70,6 +98,27 @@ reg = <3>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x000000f0>; + d-cache-size = <0x8000>; // 32KiB + d-cache-line-size = <64>;// Data side cache line length of 64 bytes + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; // 32KiB + i-cache-line-size = <64>;// Instruction side cache line length of 64 bytes + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + /* Source for cache-line-size + cache-sets + * https://developer.arm.com/documentation/ddi0500 + * /e/level-2-memory-system/about-the-l2-memory-system?lang=en + * Source for cache-size + * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf + */ + compatible = "cache"; + cache-size = <0x80000>; // 512KiB + cache-line-size = <64>; // Fixed line length of 64 bytes + cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set + cache-level = <2>; }; }; };