From patchwork Tue Dec 21 22:48:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Schleich X-Patchwork-Id: 12697027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CDB76C433EF for ; Tue, 21 Dec 2021 22:51:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date:Subject:Cc:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=ZTeOYCBoU0AmD2WxDHTT+rIwZptDjF+BWlWCfAkLUaY=; b=gS1vZ/qcUzEwjM eFl0RVZKRm9MAKpd2DbYKFH1YBtvC3Wq5ZMJoo5YVckXYTKxBO6a3HsIi+Ld38xW292nUGGOboNtc UUAxKiKJItyJSMo9CJhSAVuqGDiOt3jvahGG1NQ49ebb3vvz2wcBY43lPkzWsX/IH5zKdbSJ70S6B p4S4AgpF+6JhR+MtooHI8/Yro7gTMs0n4sPd62Fc/SvYrEcEDf+3+oxOaUMEjG9/FsoWAcImV8Pd3 tTKrTKkIYcHf2NBMtkaC0Oqi7U0utTGp7sXvwsA8bnE30PMDvyb+l5NcYQT0C7vXuj8xPNNat7u8q atGf16SNPNwcgO9Npq0A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mznwy-008fNZ-5K; Tue, 21 Dec 2021 22:49:40 +0000 Received: from mail.noreya.tech ([46.38.236.86]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mznwt-008fEX-3O; Tue, 21 Dec 2021 22:49:37 +0000 Received: from localhost (localhost [127.0.0.1]) by mail.noreya.tech (Postfix) with ESMTP id 81F6C43A; Tue, 21 Dec 2021 23:49:14 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=noreya.tech; s=s2048; t=1640126954; bh=8MSg8JYOEwSbXzLEjg2qk0EvfWpMkhElUFOoqPZUN4I=; h=From:To:Cc:Subject:Date:From; b=WlcQLymJHjxB05mVfLRKejeDHwe3p9MQBsVyGa61zf+soTZPrFZ2pztk2AsHOk2fZ DGrRPhXe085oAeZjsQF9gwZK3Zw7oDOjJ4DrR5vNxd9OdW/gV25wdWj8bREh4pwR6H 1AvSeDUv6S2VHnJYMGkBJGUjvRu7p8AvEOVcaaGMEuLnSEHKA2H011CcuQiwJW+6Q9 0WUrUb5nltF1dWqbzHYnbIbhJu9qWkS6apKYITkic+7VS772/nSlk/ruLq/Ut2KD/L 3DnHnIR+HQjoqgFgEUz08pB8OrD3Ry0nNTczl/WTdkEvgjSXnGwG4vg0hfud13tF/8 uLxSTRhR6EQ2Q== X-Virus-Scanned: Debian amavisd-new at mail.noreya.tech Received: from mail.noreya.tech ([127.0.0.1]) by localhost (mail.noreya.tech [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id ljV9xXx99KjW; Tue, 21 Dec 2021 23:49:11 +0100 (CET) Received: from richard-AX370.lan (unknown [IPv6:2a02:1748:dd5c:72f0:d99e:3050:a76:285d]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mail.noreya.tech (Postfix) with ESMTPSA; Tue, 21 Dec 2021 23:49:11 +0100 (CET) From: Richard Schleich To: robh+dt@kernel.org, nsaenz@kernel.org, f.fainelli@gmail.com, bcm-kernel-feedback-list@broadcom.com, devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org Cc: Richard Schleich Subject: [PATCH] ARM: dts: bcm2711: Add the missing L1/L2 cache information Date: Tue, 21 Dec 2021 23:48:30 +0100 Message-Id: <20211221224830.16746-1-rs@noreya.tech> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211221_144935_484077_AE40B586 X-CRM114-Status: GOOD ( 10.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch fixes the kernel warning "cacheinfo: Unable to detect cache hierarchy for CPU 0" for the bcm2711 on newer kernel versions. Signed-off-by: Richard Schleich Tested-by: Stefan Wahren --- arch/arm/boot/dts/bcm2711.dtsi | 50 ++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi index 9e01dbca4a01..b2f403fc420c 100644 --- a/arch/arm/boot/dts/bcm2711.dtsi +++ b/arch/arm/boot/dts/bcm2711.dtsi @@ -458,12 +458,26 @@ #size-cells = <0>; enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit + /* Source for d/i-cache-line-size and d/i-cache-sets + * https://developer.arm.com/documentation/100095/0003 + * /Level-1-Memory-System/About-the-L1-memory-system?lang=en + * Source for d/i-cache-size + * https://www.raspberrypi.com/documentation/computers + * /processors.html#bcm2711 + */ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x000000d8>; + d-cache-size = <0x8000>; // 32KB 2-way set-associative data cache + d-cache-line-size = <64>;// Fixed line length of 64 bytes + d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + i-cache-size = <0xc000>; // 48kB 3-way set-associative data cache + i-cache-line-size = <64>;// Fixed line length of 64 bytes + i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set + next-level-cache = <&l2>; }; cpu1: cpu@1 { @@ -472,6 +486,13 @@ reg = <1>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x000000e0>; + d-cache-size = <0x8000>; // 32KB 2-way set-associative data cache + d-cache-line-size = <64>;// Fixed line length of 64 bytes + d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + i-cache-size = <0xc000>; // 48kB 3-way set-associative data cache + i-cache-line-size = <64>;// Fixed line length of 64 bytes + i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set + next-level-cache = <&l2>; }; cpu2: cpu@2 { @@ -480,6 +501,13 @@ reg = <2>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x000000e8>; + d-cache-size = <0x8000>; // 32KB 2-way set-associative data cache + d-cache-line-size = <64>;// Fixed line length of 64 bytes + d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + i-cache-size = <0xc000>; // 48kB 3-way set-associative data cache + i-cache-line-size = <64>;// Fixed line length of 64 bytes + i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set + next-level-cache = <&l2>; }; cpu3: cpu@3 { @@ -488,6 +516,28 @@ reg = <3>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x000000f0>; + d-cache-size = <0x8000>; // 32KB 2-way set-associative data cache + d-cache-line-size = <64>;// Fixed line length of 64 bytes + d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + i-cache-size = <0xc000>; // 48kB 3-way set-associative data cache + i-cache-line-size = <64>;// Fixed line length of 64 bytes + i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + /* Source for d/i-cache-line-size and d/i-cache-sets + * https://developer.arm.com/documentation/100095/0003 + * /Level-2-Memory-System/About-the-L2-memory-system?lang=en + * Source for d/i-cache-size + * https://www.raspberrypi.com/documentation/computers + * /processors.html#bcm2711 + */ + compatible = "cache"; + cache-size = <0x100000>; // 1MB + cache-line-size = <64>; // Fixed line length of 64 bytes + cache-sets = <1024>; // 1MiB(size)/64(line-size)=16000ways/16-way set + cache-level = <2>; }; };