From patchwork Thu Jan 6 04:26:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12705114 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 910F4C433EF for ; Thu, 6 Jan 2022 04:33:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=ULBYy1/22ITneH0r7ebqcZaDZB2rViOWwbcpFMuka5s=; b=bMdJk4145bDCvaGClB1yjQ1gRo rjUgrjaABM9eUOyABlqwHTV0SCYdQOqH982n4sfAtKMe0kLTwCi/7JjwTU2fU/3QdFwgPqUgVymof h8QZFHHH/6oCS7h0jZPqLBfaJBu1NE5H2c+6e5jN6BIV51oYB/UyQtMwvBy8BbVUXxjTALMwILZ0S NCnprA6NPxulOkoyxD2daWMz6gCiN66LcsMsOiPR3EmbFbq2xYCL4iCHI0YBGnLPLL3LcvHw3+Slk XEUYH71Ngn3tcmU1FfcniSF67fq1dSVF0KcpJq+NW6G51b1td/Nf5KAi6cXQRey29tKQrBb5L3dVj Mbrm/44w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5KRl-00GTjw-1J; Thu, 06 Jan 2022 04:32:17 +0000 Received: from mail-pg1-x54a.google.com ([2607:f8b0:4864:20::54a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5KOO-00GRub-P9 for linux-arm-kernel@lists.infradead.org; Thu, 06 Jan 2022 04:28:50 +0000 Received: by mail-pg1-x54a.google.com with SMTP id t28-20020a63955c000000b0033f3b16a931so869717pgn.4 for ; Wed, 05 Jan 2022 20:28:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=kduJ8W7D23BHwaQqjKYPNo6TWtKwdbe4Pc0zb3RITt8=; b=fKlXAux6G7PjhGP2oJRAOU0jZOCiN6+OnCweQVroA6ACLMYmdQ3VyAoWtutcib5ZKj 30QA6RUJpRG8JzLhKgPmimoHkW4yLy+UKVHqwu90LnsGQus1oYaHJ7UhFlFcSPBSUuzX mUI+n7ioNGsSvMe7aR8nT5ag1xqNVpQ+B+/6e/wP4y9NuwHejlv5akE1DtvgVnntXB9R 9rtnO0Q5HTSinZbv31ZjvBKELAXybcYQhRLY6V5jvJQG0dBOT7r1LjeB6VXxgBLyzPnf 8sp/96HX8tzitwF+hgIgruNcOvCJwhT0AM2x9Pt4phAKqk3bgRnW1i6tImUBprVoRkA6 4fEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=kduJ8W7D23BHwaQqjKYPNo6TWtKwdbe4Pc0zb3RITt8=; b=o3Rq062tjYAFL66izDKJEqyP8qGnWvotPJTH9f4VDcSr+nE+MwGWh8f1iib12vpYm5 5mrOiILXaFxYDw5YAReY1VVruzuQMy+Yht5JV036xlARaYWITuJD0+2b0AiivoTAYZAH 9PPzChHhrzTw3q4xLVNT2aRPQvA6vPcigCBYS4gsx900G8yTwsiRxJO3iA2qzZjq7suI rTfBSqQwFt7BL141qm2laDhdw29jwkAEiej7c0P8fIjaI++iOGM6V2jLqPabVV9xKR9h HC7ZyZRMVYvTD9d3UY7R23KrF9bM8ipHgXtQ2canl5INt9ntJs3SaynvbiA5v7Qu4nX+ n9gw== X-Gm-Message-State: AOAM530aR7NiaiuxAvy+gedtdtH7gF7hKatqFqjHqNLIu59Js44JoBhm sy9YTBZ4qKJrbDK9nvx/7LSXs7IjBWw= X-Google-Smtp-Source: ABdhPJzPTNL48G0HNzxfO0ns7AexR+6gb/acsiG8g9dhMwIoRkX3C10ON5Y8LUKx4GNdP776NLQAWlwRwGo= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a17:90a:6d23:: with SMTP id z32mr7912129pjj.144.1641443327365; Wed, 05 Jan 2022 20:28:47 -0800 (PST) Date: Wed, 5 Jan 2022 20:26:53 -0800 In-Reply-To: <20220106042708.2869332-1-reijiw@google.com> Message-Id: <20220106042708.2869332-12-reijiw@google.com> Mime-Version: 1.0 References: <20220106042708.2869332-1-reijiw@google.com> X-Mailer: git-send-email 2.34.1.448.ga2b2bfdf31-goog Subject: [RFC PATCH v4 11/26] KVM: arm64: Make ID_DFR0_EL1 writable From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220105_202848_899732_1C053769 X-CRM114-Status: GOOD ( 17.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds id_reg_info for ID_DFR0_EL1 to make it writable by userspace. Return an error if userspace tries to set PerfMon field of the register to a value that conflicts with the PMU configuration. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/sys_regs.c | 55 ++++++++++++++++++++++++++++++++------- 1 file changed, 45 insertions(+), 10 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 9a9055d60223..1707c7832593 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -596,6 +596,27 @@ static int validate_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, return 0; } +static int validate_id_dfr0_el1(struct kvm_vcpu *vcpu, + const struct id_reg_info *id_reg, u64 val) +{ + bool vcpu_pmu, dfr0_pmu; + unsigned int perfmon; + + perfmon = cpuid_feature_extract_unsigned_field(val, ID_DFR0_PERFMON_SHIFT); + if (perfmon == 1 || perfmon == 2) + /* PMUv1 or PMUv2 is not allowed on ARMv8. */ + return -EINVAL; + + vcpu_pmu = kvm_vcpu_has_pmu(vcpu); + dfr0_pmu = id_reg_has_pmu(val, ID_DFR0_PERFMON_SHIFT, ID_DFR0_PERFMON_8_0); + + /* Check if there is a conflict with a request via KVM_ARM_VCPU_INIT */ + if (vcpu_pmu ^ dfr0_pmu) + return -EPERM; + + return 0; +} + static void init_id_aa64pfr0_el1_info(struct id_reg_info *id_reg) { u64 limit = id_reg->vcpu_limit_val; @@ -656,8 +677,17 @@ static void init_id_aa64dfr0_el1_info(struct id_reg_info *id_reg) id_reg->vcpu_limit_val = limit; } +static void init_id_dfr0_el1_info(struct id_reg_info *id_reg) +{ + /* Limit guests to PMUv3 for ARMv8.4 */ + id_reg->vcpu_limit_val = + cpuid_feature_cap_perfmon_field(id_reg->vcpu_limit_val, + ID_DFR0_PERFMON_SHIFT, + ID_DFR0_PERFMON_8_4); +} + static u64 vcpu_mask_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, - const struct id_reg_info *idr) + const struct id_reg_info *idr) { return vcpu_has_sve(vcpu) ? 0 : ARM64_FEATURE_MASK(ID_AA64PFR0_SVE); } @@ -680,6 +710,12 @@ static u64 vcpu_mask_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, return kvm_vcpu_has_pmu(vcpu) ? 0 : ARM64_FEATURE_MASK(ID_AA64DFR0_PMUVER); } +static u64 vcpu_mask_id_dfr0_el1(const struct kvm_vcpu *vcpu, + const struct id_reg_info *idr) +{ + return kvm_vcpu_has_pmu(vcpu) ? 0 : ARM64_FEATURE_MASK(ID_DFR0_PERFMON); +} + static struct id_reg_info id_aa64pfr0_el1_info = { .sys_reg = SYS_ID_AA64PFR0_EL1, .ignore_mask = ARM64_FEATURE_MASK(ID_AA64PFR0_GIC), @@ -731,6 +767,13 @@ static struct id_reg_info id_aa64dfr0_el1_info = { .vcpu_mask = vcpu_mask_id_aa64dfr0_el1, }; +static struct id_reg_info id_dfr0_el1_info = { + .sys_reg = SYS_ID_DFR0_EL1, + .init = init_id_dfr0_el1_info, + .validate = validate_id_dfr0_el1, + .vcpu_mask = vcpu_mask_id_dfr0_el1, +}; + /* * An ID register that needs special handling to control the value for the * guest must have its own id_reg_info in id_reg_info_table. @@ -740,6 +783,7 @@ static struct id_reg_info id_aa64dfr0_el1_info = { */ #define GET_ID_REG_INFO(id) (id_reg_info_table[IDREG_IDX(id)]) static struct id_reg_info *id_reg_info_table[KVM_ARM_ID_REG_MAX_NUM] = { + [IDREG_IDX(SYS_ID_DFR0_EL1)] = &id_dfr0_el1_info, [IDREG_IDX(SYS_ID_AA64PFR0_EL1)] = &id_aa64pfr0_el1_info, [IDREG_IDX(SYS_ID_AA64PFR1_EL1)] = &id_aa64pfr1_el1_info, [IDREG_IDX(SYS_ID_AA64DFR0_EL1)] = &id_aa64dfr0_el1_info, @@ -1662,15 +1706,6 @@ static u64 __read_id_reg(const struct kvm_vcpu *vcpu, u32 id) /* Clear fields for opt-in features that are not configured. */ val &= ~(id_reg->vcpu_mask(vcpu, id_reg)); - switch (id) { - case SYS_ID_DFR0_EL1: - /* Limit guests to PMUv3 for ARMv8.4 */ - val = cpuid_feature_cap_perfmon_field(val, - ID_DFR0_PERFMON_SHIFT, - kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0); - break; - } - return val; }