From patchwork Fri Jan 7 23:53:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 12707149 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A8239C433F5 for ; Fri, 7 Jan 2022 23:55:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Xjcp7qOGEUDa6tiJYWRSp4wk25f8RlhBY4LSYw5pcnk=; b=ddUe/XosXSaqmh ftcLG15Ggc0r6539YiT/MY67bOA+PtlgkviftMsUiODyqJMFquZnk4c3qDCVn5Y86T0QCmani4iz1 DhbD7aLtL8Z9XN+EAnpbWJPGkXQFPV2wvAy51O6URc2/KtUKlQVd0cfOetziE7ZWHDt1jDkCsIv7S JMNRy2g6EfsZcJnTFtRjiXMih9eASK8CN812N4k+1QQUVx83ekXT0SIumFRYWLclWZpHSoOXQkxS2 AHB1T8e613IUP52OGV3oSriu4MKEYpAUe2Fp+EjzddtaeipX0v0w+xth6UPWDegraFy873XqaSYp0 tBhiayZZMoFmgRqs1aVw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5z3m-005Z68-N2; Fri, 07 Jan 2022 23:54:14 +0000 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5z38-005Ykr-L0 for linux-arm-kernel@lists.infradead.org; Fri, 07 Jan 2022 23:53:37 +0000 Received: by mail-pf1-x436.google.com with SMTP id v13so6517844pfi.3 for ; Fri, 07 Jan 2022 15:53:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EC6Yy1tAZPwKkwKJYGHE/vqhf31r7sL2lK9QflxCMkc=; b=l6MDdTSWAeTxNGvEd93nFWHohs6kDg+tWO7s+yzY75uQRjE/BUZL1kjNK+KjgI9a9t aPx/i6Iaen1SS2wobC8fW5PqQBGs6sokNQFaN+A0zHsO5gxsScGMZ1kAu4i9Dn7irHmw FyyZCrIBRJwc3h2FllmUT1etPGBlGUa7w0YSk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EC6Yy1tAZPwKkwKJYGHE/vqhf31r7sL2lK9QflxCMkc=; b=SeLC6r4b6OdM/uzzsQOod5anXJnfO0fhKY6zU3uXSu8Qzu6wdSh+M5J+LbHGlFV2JW OErBPYTp281UjZ2+gARhcMK+NsWC0grXe69Gmb91A6pIZyhiwq/UDAk7rCHoikuTMd3S YuZLjJxgFO0jXUmXnageJMb6iZWxAqBgNQznu87QH5a5jciYRpMA+5qNqd3Z5LOuuVS6 UcEsm1FgP5pw3vJ5R9OAkOUO3Scse8h+sEp8SDCDNPmqxMK3SCjOao+GOt904MzB5YGC qsmLcwYrMziYXKYqiu2GY1t7zS+9/cXhkB5k7wZUYMeujwjaEchrMsXqN4ITGJAfUCsB 1XEg== X-Gm-Message-State: AOAM531gzRjrYM0+55UHS9iLCZVpJPKyTk7Ff3Cg8dPlOQU2+GGf9OBm ZIMstH8RODNsY0wJ5AVSMjfITw== X-Google-Smtp-Source: ABdhPJz/zuh06SfcYdI8C2pwHxKqrqYVX1iKu5qlgzfHoSrOLowcEYEFERoS9ljANAwquYdmLD+jnQ== X-Received: by 2002:aa7:9799:0:b0:4bd:49ce:8bb1 with SMTP id o25-20020aa79799000000b004bd49ce8bb1mr555903pfp.74.1641599613569; Fri, 07 Jan 2022 15:53:33 -0800 (PST) Received: from localhost ([2620:15c:202:201:db:1c60:693f:c24e]) by smtp.gmail.com with UTF8SMTPSA id s12sm43682pfk.220.2022.01.07.15.53.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 07 Jan 2022 15:53:33 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: Heiko Stuebner , linux-arm-kernel@lists.infradead.org, Lin Huang , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-pm@vger.kernel.org, Derek Basehore , linux-kernel@vger.kernel.org, Brian Norris Subject: [PATCH 02/10] dt-bindings: devfreq: rk3399_dmc: Deprecate unused/redundant properties Date: Fri, 7 Jan 2022 15:53:12 -0800 Message-Id: <20220107155215.2.I5ba582cd678d34c03d647e5500db8e33b7524d66@changeid> X-Mailer: git-send-email 2.34.1.575.g55b058a8bb-goog In-Reply-To: <20220107235320.965497-1-briannorris@chromium.org> References: <20220107235320.965497-1-briannorris@chromium.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220107_155334_733757_EABA1B76 X-CRM114-Status: GOOD ( 13.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org These DRAM configuration properties are all handled in ARM Trusted Firmware (and have been since the early days of this SoC), and there are no in-tree users of the DMC binding yet. It's better to just defer to firmware instead of maintaining this large list of properties. There's also some confusion about units: many of these are specified in MHz, but the downstream users and driver code are treating them as Hz, I believe. Rather than straighten all that out, I just drop them. Signed-off-by: Brian Norris Reviewed-by: Rob Herring --- .../bindings/devfreq/rk3399_dmc.yaml | 42 +++++++++---------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml index f12f34d93378..6bb411dddb7b 100644 --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml @@ -58,6 +58,7 @@ properties: finishes a DCF interrupt is triggered. rockchip,ddr3_speed_bin: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: For values, reference include/dt-bindings/clock/rk3399-ddr.h. Selects the @@ -104,6 +105,7 @@ properties: if bus is idle for standby_idle * DFI clock cycles. rockchip,dram_dll_dis_freq: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: | Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less @@ -111,6 +113,7 @@ properties: Note: if DLL was bypassed, the odt will also stop working. rockchip,phy_dll_dis_freq: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: | Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency @@ -118,6 +121,7 @@ properties: Note: PHY DLL and PHY ODT are independent. rockchip,auto_pd_dis_freq: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: Defines the auto PD disable frequency in MHz. @@ -131,18 +135,21 @@ properties: disabled. rockchip,ddr3_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the DRAM side drive strength in ohms. Default value is 40. rockchip,ddr3_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the DRAM side ODT strength in ohms. Default value is 120. rockchip,phy_ddr3_ca_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the phy side CA line @@ -150,12 +157,14 @@ properties: Default value is 40. rockchip,phy_ddr3_dq_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the PHY side DQ line (including DQS/DQ/DM line) drive strength. Default value is 40. rockchip,phy_ddr3_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the PHY side ODT @@ -170,18 +179,21 @@ properties: disabled. rockchip,lpddr3_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR3, this parameter defines the DRAM side drive strength in ohms. Default value is 34. rockchip,lpddr3_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT strength in ohms. Default value is 240. rockchip,phy_lpddr3_ca_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR3, this parameter defines the PHY side CA line @@ -189,12 +201,14 @@ properties: Default value is 40. rockchip,phy_lpddr3_dq_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line (including DQS/DQ/DM line) drive strength. Default value is 40. rockchip,phy_lpddr3_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When dram type is LPDDR3, this parameter define the phy side odt @@ -209,42 +223,49 @@ properties: disabled. rockchip,lpddr4_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the DRAM side drive strength in ohms. Default value is 60. rockchip,lpddr4_dq_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on DQS/DQ line strength in ohms. Default value is 40. rockchip,lpddr4_ca_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on CA line strength in ohms. Default value is 40. rockchip,phy_lpddr4_ca_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the PHY side CA line (including command address line) drive strength. Default value is 40. rockchip,phy_lpddr4_ck_cs_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the PHY side clock line and CS line drive strength. Default value is 80. rockchip,phy_lpddr4_dq_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line (including DQS/DQ/DM line) drive strength. Default value is 80. rockchip,phy_lpddr4_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the PHY side ODT @@ -265,33 +286,12 @@ examples: clock-names = "dmc_clk"; operating-points-v2 = <&dmc_opp_table>; center-supply = <&ppvar_centerlogic>; - rockchip,ddr3_speed_bin = <21>; rockchip,pd_idle = <0x40>; rockchip,sr_idle = <0x2>; rockchip,sr_mc_gate_idle = <0x3>; rockchip,srpd_lite_idle = <0x4>; rockchip,standby_idle = <0x2000>; - rockchip,dram_dll_dis_freq = <300>; - rockchip,phy_dll_dis_freq = <125>; - rockchip,auto_pd_dis_freq = <666>; rockchip,ddr3_odt_dis_freq = <333>; - rockchip,ddr3_drv = <40>; - rockchip,ddr3_odt = <120>; - rockchip,phy_ddr3_ca_drv = <40>; - rockchip,phy_ddr3_dq_drv = <40>; - rockchip,phy_ddr3_odt = <240>; rockchip,lpddr3_odt_dis_freq = <333>; - rockchip,lpddr3_drv = <34>; - rockchip,lpddr3_odt = <240>; - rockchip,phy_lpddr3_ca_drv = <40>; - rockchip,phy_lpddr3_dq_drv = <40>; - rockchip,phy_lpddr3_odt = <240>; rockchip,lpddr4_odt_dis_freq = <333>; - rockchip,lpddr4_drv = <60>; - rockchip,lpddr4_dq_odt = <40>; - rockchip,lpddr4_ca_odt = <40>; - rockchip,phy_lpddr4_ca_drv = <40>; - rockchip,phy_lpddr4_ck_cs_drv = <80>; - rockchip,phy_lpddr4_dq_drv = <80>; - rockchip,phy_lpddr4_odt = <60>; };