From patchwork Tue Jan 11 13:06:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 12709850 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3F9D7C433EF for ; Tue, 11 Jan 2022 13:08:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=nJ/LGPP53ts18jY/LvQ+oe22+Ij+b4ay+fhz/t71tR4=; b=qhoesYOAqZx8GL cKnUfd7abFG4pUscYp34OBklVX6awZOOgiyUpFipjioEJS5qo3alz+2Bs70vG01Swwqxcju7/6DS3 V5yhwf4t71U6P3Eykuo8VHjQOhAP8jSOTmlNLUOPcFSIZ0OBPzUvdOo+GpKKi/CkAu36RmtxuEi5Y Y1YRHG+CrD52AG+wEHruS9GkFpjFi35q8lD8Alm04EJYbbxiRDG9guxptfvpSdpeEKQeyVYB1s2p6 wDy8o8+5qAL8BGfJ9lCGkX2l/328oiHcufmxr1Vh9Je+qT2rZjLBAsqoceT045ce/bL/w1soXqhEx sBDrSaNAqVLRfTywAM4w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n7Gs8-00GIMq-Qf; Tue, 11 Jan 2022 13:07:32 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n7Grm-00GIDk-Jo for linux-arm-kernel@lists.infradead.org; Tue, 11 Jan 2022 13:07:12 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A30A6106F; Tue, 11 Jan 2022 05:07:09 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D7FD73F774; Tue, 11 Jan 2022 05:07:08 -0800 (PST) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: andre.przywara@arm.com, Jaxson.Han@arm.com, mark.rutland@arm.com, Wei.Chen@arm.com Subject: [bootwrapper PATCH 03/13] aarch64: add system register accessors Date: Tue, 11 Jan 2022 13:06:43 +0000 Message-Id: <20220111130653.2331827-4-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220111130653.2331827-1-mark.rutland@arm.com> References: <20220111130653.2331827-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220111_050710_766272_0DC51E01 X-CRM114-Status: UNSURE ( 9.85 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org We open code the use of mrs/msr for specific registers, which is somewhat tedious. Add macros to do this generically, along with a helper to extract a specific register field. Existing C usage is converted to the new helpers, and register definitions moved to a common location. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland --- arch/aarch64/include/asm/cpu.h | 41 ++++++++++++++++++++++--------- arch/aarch64/include/asm/gic-v3.h | 10 +++----- 2 files changed, 32 insertions(+), 19 deletions(-) diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 63eb1c3..1053414 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -9,10 +9,14 @@ #ifndef __ASM_AARCH64_CPU_H #define __ASM_AARCH64_CPU_H +#include + #define MPIDR_ID_BITS 0xff00ffffff #define CURRENTEL_EL3 (3 << 2) +#define ID_AA64PFR0_EL1_GIC BITS(27, 24) + /* * RES1 bits, little-endian, caches and MMU off, no alignment checking, * no WXN. @@ -29,6 +33,12 @@ #define CPTR_EL3_EZ (1 << 8) +#define ICC_SRE_EL2 S3_4_C12_C9_5 +#define ICC_SRE_EL3 S3_6_C12_C12_5 +#define ICC_CTLR_EL1 S3_0_C12_C12_4 +#define ICC_CTLR_EL3 S3_6_C12_C12_4 +#define ICC_PMR_EL1 S3_0_C4_C6_0 + #define ZCR_EL3 s3_6_c1_c2_0 #define ZCR_EL3_LEN_MASK 0x1ff @@ -50,20 +60,27 @@ #define sevl() asm volatile ("sevl\n" : : : "memory") -static inline unsigned long read_mpidr(void) -{ - unsigned long mpidr; +#define __str(def) #def - asm volatile ("mrs %0, mpidr_el1\n" : "=r" (mpidr)); - return mpidr & MPIDR_ID_BITS; -} +#define mrs(reg) \ +({ \ + unsigned long __mrs_val; \ + asm volatile("mrs %0, " __str(reg) : "=r" (__mrs_val)); \ + __mrs_val; \ +}) -static inline uint64_t read_id_aa64pfr0(void) -{ - uint64_t val; +#define msr(reg, val) \ +do { \ + unsigned long __msr_val = val; \ + asm volatile("msr " __str(reg) ", %0" : : "r" (__msr_val)); \ +} while (0) + +#define mrs_field(reg, field) \ + BITS_EXTRACT(mrs(reg), (reg##_##field)) - asm volatile ("mrs %0, id_aa64pfr0_el1\n" : "=r" (val)); - return val; +static inline unsigned long read_mpidr(void) +{ + return mrs(mpidr_el1) & MPIDR_ID_BITS; } static inline void iciallu(void) @@ -73,7 +90,7 @@ static inline void iciallu(void) static inline int has_gicv3_sysreg(void) { - return !!((read_id_aa64pfr0() >> 24) & 0xf); + return !!mrs_field(ID_AA64PFR0_EL1, GIC); } #endif /* !__ASSEMBLY__ */ diff --git a/arch/aarch64/include/asm/gic-v3.h b/arch/aarch64/include/asm/gic-v3.h index 5b32380..2447480 100644 --- a/arch/aarch64/include/asm/gic-v3.h +++ b/arch/aarch64/include/asm/gic-v3.h @@ -9,20 +9,16 @@ #ifndef __ASM_AARCH64_GICV3_H #define __ASM_AARCH64_GICV3_H -#define ICC_SRE_EL2 "S3_4_C12_C9_5" -#define ICC_SRE_EL3 "S3_6_C12_C12_5" -#define ICC_CTLR_EL1 "S3_0_C12_C12_4" -#define ICC_CTLR_EL3 "S3_6_C12_C12_4" -#define ICC_PMR_EL1 "S3_0_C4_C6_0" +#include static inline void gic_write_icc_sre(uint32_t val) { - asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val)); + msr(ICC_SRE_EL3, val); } static inline void gic_write_icc_ctlr(uint32_t val) { - asm volatile ("msr " ICC_CTLR_EL3 ", %0" : : "r" (val)); + msr(ICC_CTLR_EL3, val); } #endif