| Message ID | 20220112151814.24361-12-pali@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | PCI: mvebu: subsystem ids, AER and INTx | expand |
Hello Pali, > With this change legacy INTA, INTB, INTC and INTD interrupts are reported > separately and not mixed into one Linux virq source anymore. > > Signed-off-by: Pali Rohár <pali@kernel.org> > --- > arch/arm/boot/dts/armada-385.dtsi | 52 ++++++++++++++++++++++++++----- Is there any reason for not doing the same change in armada-380.dtsi ? Grégory > 1 file changed, 44 insertions(+), 8 deletions(-) > > diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi > index f0022d10c715..83392b92dae2 100644 > --- a/arch/arm/boot/dts/armada-385.dtsi > +++ b/arch/arm/boot/dts/armada-385.dtsi > @@ -69,16 +69,25 @@ > reg = <0x0800 0 0 0 0>; > #address-cells = <3>; > #size-cells = <2>; > + interrupt-names = "intx"; > + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; > #interrupt-cells = <1>; > ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 > 0x81000000 0 0 0x81000000 0x1 0 1 0>; > bus-range = <0x00 0xff>; > - interrupt-map-mask = <0 0 0 0>; > - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie1_intc 0>, > + <0 0 0 2 &pcie1_intc 1>, > + <0 0 0 3 &pcie1_intc 2>, > + <0 0 0 4 &pcie1_intc 3>; > marvell,pcie-port = <0>; > marvell,pcie-lane = <0>; > clocks = <&gateclk 8>; > status = "disabled"; > + pcie1_intc: interrupt-controller { > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > }; > > /* x1 port */ > @@ -88,16 +97,25 @@ > reg = <0x1000 0 0 0 0>; > #address-cells = <3>; > #size-cells = <2>; > + interrupt-names = "intx"; > + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > #interrupt-cells = <1>; > ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 > 0x81000000 0 0 0x81000000 0x2 0 1 0>; > bus-range = <0x00 0xff>; > - interrupt-map-mask = <0 0 0 0>; > - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie2_intc 0>, > + <0 0 0 2 &pcie2_intc 1>, > + <0 0 0 3 &pcie2_intc 2>, > + <0 0 0 4 &pcie2_intc 3>; > marvell,pcie-port = <1>; > marvell,pcie-lane = <0>; > clocks = <&gateclk 5>; > status = "disabled"; > + pcie2_intc: interrupt-controller { > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > }; > > /* x1 port */ > @@ -107,16 +125,25 @@ > reg = <0x1800 0 0 0 0>; > #address-cells = <3>; > #size-cells = <2>; > + interrupt-names = "intx"; > + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > #interrupt-cells = <1>; > ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 > 0x81000000 0 0 0x81000000 0x3 0 1 0>; > bus-range = <0x00 0xff>; > - interrupt-map-mask = <0 0 0 0>; > - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie3_intc 0>, > + <0 0 0 2 &pcie3_intc 1>, > + <0 0 0 3 &pcie3_intc 2>, > + <0 0 0 4 &pcie3_intc 3>; > marvell,pcie-port = <2>; > marvell,pcie-lane = <0>; > clocks = <&gateclk 6>; > status = "disabled"; > + pcie3_intc: interrupt-controller { > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > }; > > /* > @@ -129,16 +156,25 @@ > reg = <0x2000 0 0 0 0>; > #address-cells = <3>; > #size-cells = <2>; > + interrupt-names = "intx"; > + interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > #interrupt-cells = <1>; > ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 > 0x81000000 0 0 0x81000000 0x4 0 1 0>; > bus-range = <0x00 0xff>; > - interrupt-map-mask = <0 0 0 0>; > - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie4_intc 0>, > + <0 0 0 2 &pcie4_intc 1>, > + <0 0 0 3 &pcie4_intc 2>, > + <0 0 0 4 &pcie4_intc 3>; > marvell,pcie-port = <3>; > marvell,pcie-lane = <0>; > clocks = <&gateclk 7>; > status = "disabled"; > + pcie4_intc: interrupt-controller { > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > }; > }; > }; > -- > 2.20.1 >
On Monday 14 February 2022 16:07:13 Gregory CLEMENT wrote: > Hello Pali, > > > With this change legacy INTA, INTB, INTC and INTD interrupts are reported > > separately and not mixed into one Linux virq source anymore. > > > > Signed-off-by: Pali Rohár <pali@kernel.org> > > --- > > arch/arm/boot/dts/armada-385.dtsi | 52 ++++++++++++++++++++++++++----- > > Is there any reason for not doing the same change in armada-380.dtsi ? I do not have A380 HW, so I did this change only for A385 which I have tested. > Grégory > > > 1 file changed, 44 insertions(+), 8 deletions(-) > > > > diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi > > index f0022d10c715..83392b92dae2 100644 > > --- a/arch/arm/boot/dts/armada-385.dtsi > > +++ b/arch/arm/boot/dts/armada-385.dtsi > > @@ -69,16 +69,25 @@ > > reg = <0x0800 0 0 0 0>; > > #address-cells = <3>; > > #size-cells = <2>; > > + interrupt-names = "intx"; > > + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; > > #interrupt-cells = <1>; > > ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 > > 0x81000000 0 0 0x81000000 0x1 0 1 0>; > > bus-range = <0x00 0xff>; > > - interrupt-map-mask = <0 0 0 0>; > > - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-map-mask = <0 0 0 7>; > > + interrupt-map = <0 0 0 1 &pcie1_intc 0>, > > + <0 0 0 2 &pcie1_intc 1>, > > + <0 0 0 3 &pcie1_intc 2>, > > + <0 0 0 4 &pcie1_intc 3>; > > marvell,pcie-port = <0>; > > marvell,pcie-lane = <0>; > > clocks = <&gateclk 8>; > > status = "disabled"; > > + pcie1_intc: interrupt-controller { > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + }; > > }; > > > > /* x1 port */ > > @@ -88,16 +97,25 @@ > > reg = <0x1000 0 0 0 0>; > > #address-cells = <3>; > > #size-cells = <2>; > > + interrupt-names = "intx"; > > + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > > #interrupt-cells = <1>; > > ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 > > 0x81000000 0 0 0x81000000 0x2 0 1 0>; > > bus-range = <0x00 0xff>; > > - interrupt-map-mask = <0 0 0 0>; > > - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-map-mask = <0 0 0 7>; > > + interrupt-map = <0 0 0 1 &pcie2_intc 0>, > > + <0 0 0 2 &pcie2_intc 1>, > > + <0 0 0 3 &pcie2_intc 2>, > > + <0 0 0 4 &pcie2_intc 3>; > > marvell,pcie-port = <1>; > > marvell,pcie-lane = <0>; > > clocks = <&gateclk 5>; > > status = "disabled"; > > + pcie2_intc: interrupt-controller { > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + }; > > }; > > > > /* x1 port */ > > @@ -107,16 +125,25 @@ > > reg = <0x1800 0 0 0 0>; > > #address-cells = <3>; > > #size-cells = <2>; > > + interrupt-names = "intx"; > > + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > > #interrupt-cells = <1>; > > ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 > > 0x81000000 0 0 0x81000000 0x3 0 1 0>; > > bus-range = <0x00 0xff>; > > - interrupt-map-mask = <0 0 0 0>; > > - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-map-mask = <0 0 0 7>; > > + interrupt-map = <0 0 0 1 &pcie3_intc 0>, > > + <0 0 0 2 &pcie3_intc 1>, > > + <0 0 0 3 &pcie3_intc 2>, > > + <0 0 0 4 &pcie3_intc 3>; > > marvell,pcie-port = <2>; > > marvell,pcie-lane = <0>; > > clocks = <&gateclk 6>; > > status = "disabled"; > > + pcie3_intc: interrupt-controller { > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + }; > > }; > > > > /* > > @@ -129,16 +156,25 @@ > > reg = <0x2000 0 0 0 0>; > > #address-cells = <3>; > > #size-cells = <2>; > > + interrupt-names = "intx"; > > + interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > > #interrupt-cells = <1>; > > ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 > > 0x81000000 0 0 0x81000000 0x4 0 1 0>; > > bus-range = <0x00 0xff>; > > - interrupt-map-mask = <0 0 0 0>; > > - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-map-mask = <0 0 0 7>; > > + interrupt-map = <0 0 0 1 &pcie4_intc 0>, > > + <0 0 0 2 &pcie4_intc 1>, > > + <0 0 0 3 &pcie4_intc 2>, > > + <0 0 0 4 &pcie4_intc 3>; > > marvell,pcie-port = <3>; > > marvell,pcie-lane = <0>; > > clocks = <&gateclk 7>; > > status = "disabled"; > > + pcie4_intc: interrupt-controller { > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + }; > > }; > > }; > > }; > > -- > > 2.20.1 > > > > -- > Gregory Clement, Bootlin > Embedded Linux and Kernel engineering > http://bootlin.com
Hello, > On Monday 14 February 2022 16:07:13 Gregory CLEMENT wrote: >> Hello Pali, >> >> > With this change legacy INTA, INTB, INTC and INTD interrupts are reported >> > separately and not mixed into one Linux virq source anymore. >> > >> > Signed-off-by: Pali Rohár <pali@kernel.org> >> > --- >> > arch/arm/boot/dts/armada-385.dtsi | 52 ++++++++++++++++++++++++++----- >> >> Is there any reason for not doing the same change in armada-380.dtsi ? > > I do not have A380 HW, so I did this change only for A385 which I have > tested. OK fair enough. So you can add my Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Moreover to keep biscetability this patch should be merged after the support in the driver. So the easier is to let merge it through the PCI subsystem with the other patches from this series. I do not think there will be any other changes in this file so there won't be any merge conflicts. Thanks, Grégory > >> Grégory >> >> > 1 file changed, 44 insertions(+), 8 deletions(-) >> > >> > diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi >> > index f0022d10c715..83392b92dae2 100644 >> > --- a/arch/arm/boot/dts/armada-385.dtsi >> > +++ b/arch/arm/boot/dts/armada-385.dtsi >> > @@ -69,16 +69,25 @@ >> > reg = <0x0800 0 0 0 0>; >> > #address-cells = <3>; >> > #size-cells = <2>; >> > + interrupt-names = "intx"; >> > + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; >> > #interrupt-cells = <1>; >> > ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 >> > 0x81000000 0 0 0x81000000 0x1 0 1 0>; >> > bus-range = <0x00 0xff>; >> > - interrupt-map-mask = <0 0 0 0>; >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; >> > + interrupt-map-mask = <0 0 0 7>; >> > + interrupt-map = <0 0 0 1 &pcie1_intc 0>, >> > + <0 0 0 2 &pcie1_intc 1>, >> > + <0 0 0 3 &pcie1_intc 2>, >> > + <0 0 0 4 &pcie1_intc 3>; >> > marvell,pcie-port = <0>; >> > marvell,pcie-lane = <0>; >> > clocks = <&gateclk 8>; >> > status = "disabled"; >> > + pcie1_intc: interrupt-controller { >> > + interrupt-controller; >> > + #interrupt-cells = <1>; >> > + }; >> > }; >> > >> > /* x1 port */ >> > @@ -88,16 +97,25 @@ >> > reg = <0x1000 0 0 0 0>; >> > #address-cells = <3>; >> > #size-cells = <2>; >> > + interrupt-names = "intx"; >> > + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; >> > #interrupt-cells = <1>; >> > ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 >> > 0x81000000 0 0 0x81000000 0x2 0 1 0>; >> > bus-range = <0x00 0xff>; >> > - interrupt-map-mask = <0 0 0 0>; >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; >> > + interrupt-map-mask = <0 0 0 7>; >> > + interrupt-map = <0 0 0 1 &pcie2_intc 0>, >> > + <0 0 0 2 &pcie2_intc 1>, >> > + <0 0 0 3 &pcie2_intc 2>, >> > + <0 0 0 4 &pcie2_intc 3>; >> > marvell,pcie-port = <1>; >> > marvell,pcie-lane = <0>; >> > clocks = <&gateclk 5>; >> > status = "disabled"; >> > + pcie2_intc: interrupt-controller { >> > + interrupt-controller; >> > + #interrupt-cells = <1>; >> > + }; >> > }; >> > >> > /* x1 port */ >> > @@ -107,16 +125,25 @@ >> > reg = <0x1800 0 0 0 0>; >> > #address-cells = <3>; >> > #size-cells = <2>; >> > + interrupt-names = "intx"; >> > + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; >> > #interrupt-cells = <1>; >> > ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 >> > 0x81000000 0 0 0x81000000 0x3 0 1 0>; >> > bus-range = <0x00 0xff>; >> > - interrupt-map-mask = <0 0 0 0>; >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; >> > + interrupt-map-mask = <0 0 0 7>; >> > + interrupt-map = <0 0 0 1 &pcie3_intc 0>, >> > + <0 0 0 2 &pcie3_intc 1>, >> > + <0 0 0 3 &pcie3_intc 2>, >> > + <0 0 0 4 &pcie3_intc 3>; >> > marvell,pcie-port = <2>; >> > marvell,pcie-lane = <0>; >> > clocks = <&gateclk 6>; >> > status = "disabled"; >> > + pcie3_intc: interrupt-controller { >> > + interrupt-controller; >> > + #interrupt-cells = <1>; >> > + }; >> > }; >> > >> > /* >> > @@ -129,16 +156,25 @@ >> > reg = <0x2000 0 0 0 0>; >> > #address-cells = <3>; >> > #size-cells = <2>; >> > + interrupt-names = "intx"; >> > + interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; >> > #interrupt-cells = <1>; >> > ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 >> > 0x81000000 0 0 0x81000000 0x4 0 1 0>; >> > bus-range = <0x00 0xff>; >> > - interrupt-map-mask = <0 0 0 0>; >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; >> > + interrupt-map-mask = <0 0 0 7>; >> > + interrupt-map = <0 0 0 1 &pcie4_intc 0>, >> > + <0 0 0 2 &pcie4_intc 1>, >> > + <0 0 0 3 &pcie4_intc 2>, >> > + <0 0 0 4 &pcie4_intc 3>; >> > marvell,pcie-port = <3>; >> > marvell,pcie-lane = <0>; >> > clocks = <&gateclk 7>; >> > status = "disabled"; >> > + pcie4_intc: interrupt-controller { >> > + interrupt-controller; >> > + #interrupt-cells = <1>; >> > + }; >> > }; >> > }; >> > }; >> > -- >> > 2.20.1 >> > >> >> -- >> Gregory Clement, Bootlin >> Embedded Linux and Kernel engineering >> http://bootlin.com
Hello, Sorry for jumping in the conversation, but I read this thread and I have an Armada A388 HW so I can test it, if desired. Luís On Tue, Feb 15, 2022 at 10:47 AM Luís Mendes <luis.p.mendes@gmail.com> wrote: > > Hello, > > Sorry for jumping in the conversation, but I read this thread and I have an Armada A388 HW so I can test it, if desired. > > Luís > > On Mon, Feb 14, 2022 at 7:57 PM Gregory CLEMENT <gregory.clement@bootlin.com> wrote: >> >> Hello, >> >> > On Monday 14 February 2022 16:07:13 Gregory CLEMENT wrote: >> >> Hello Pali, >> >> >> >> > With this change legacy INTA, INTB, INTC and INTD interrupts are reported >> >> > separately and not mixed into one Linux virq source anymore. >> >> > >> >> > Signed-off-by: Pali Rohár <pali@kernel.org> >> >> > --- >> >> > arch/arm/boot/dts/armada-385.dtsi | 52 ++++++++++++++++++++++++++----- >> >> >> >> Is there any reason for not doing the same change in armada-380.dtsi ? >> > >> > I do not have A380 HW, so I did this change only for A385 which I have >> > tested. >> >> OK fair enough. >> >> So you can add my >> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> >> >> Moreover to keep biscetability this patch should be merged after the >> support in the driver. So the easier is to let merge it through the PCI >> subsystem with the other patches from this series. I do not think there >> will be any other changes in this file so there won't be any merge >> conflicts. >> >> Thanks, >> >> Grégory >> >> >> > >> >> Grégory >> >> >> >> > 1 file changed, 44 insertions(+), 8 deletions(-) >> >> > >> >> > diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi >> >> > index f0022d10c715..83392b92dae2 100644 >> >> > --- a/arch/arm/boot/dts/armada-385.dtsi >> >> > +++ b/arch/arm/boot/dts/armada-385.dtsi >> >> > @@ -69,16 +69,25 @@ >> >> > reg = <0x0800 0 0 0 0>; >> >> > #address-cells = <3>; >> >> > #size-cells = <2>; >> >> > + interrupt-names = "intx"; >> >> > + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; >> >> > #interrupt-cells = <1>; >> >> > ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 >> >> > 0x81000000 0 0 0x81000000 0x1 0 1 0>; >> >> > bus-range = <0x00 0xff>; >> >> > - interrupt-map-mask = <0 0 0 0>; >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; >> >> > + interrupt-map-mask = <0 0 0 7>; >> >> > + interrupt-map = <0 0 0 1 &pcie1_intc 0>, >> >> > + <0 0 0 2 &pcie1_intc 1>, >> >> > + <0 0 0 3 &pcie1_intc 2>, >> >> > + <0 0 0 4 &pcie1_intc 3>; >> >> > marvell,pcie-port = <0>; >> >> > marvell,pcie-lane = <0>; >> >> > clocks = <&gateclk 8>; >> >> > status = "disabled"; >> >> > + pcie1_intc: interrupt-controller { >> >> > + interrupt-controller; >> >> > + #interrupt-cells = <1>; >> >> > + }; >> >> > }; >> >> > >> >> > /* x1 port */ >> >> > @@ -88,16 +97,25 @@ >> >> > reg = <0x1000 0 0 0 0>; >> >> > #address-cells = <3>; >> >> > #size-cells = <2>; >> >> > + interrupt-names = "intx"; >> >> > + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; >> >> > #interrupt-cells = <1>; >> >> > ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 >> >> > 0x81000000 0 0 0x81000000 0x2 0 1 0>; >> >> > bus-range = <0x00 0xff>; >> >> > - interrupt-map-mask = <0 0 0 0>; >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; >> >> > + interrupt-map-mask = <0 0 0 7>; >> >> > + interrupt-map = <0 0 0 1 &pcie2_intc 0>, >> >> > + <0 0 0 2 &pcie2_intc 1>, >> >> > + <0 0 0 3 &pcie2_intc 2>, >> >> > + <0 0 0 4 &pcie2_intc 3>; >> >> > marvell,pcie-port = <1>; >> >> > marvell,pcie-lane = <0>; >> >> > clocks = <&gateclk 5>; >> >> > status = "disabled"; >> >> > + pcie2_intc: interrupt-controller { >> >> > + interrupt-controller; >> >> > + #interrupt-cells = <1>; >> >> > + }; >> >> > }; >> >> > >> >> > /* x1 port */ >> >> > @@ -107,16 +125,25 @@ >> >> > reg = <0x1800 0 0 0 0>; >> >> > #address-cells = <3>; >> >> > #size-cells = <2>; >> >> > + interrupt-names = "intx"; >> >> > + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; >> >> > #interrupt-cells = <1>; >> >> > ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 >> >> > 0x81000000 0 0 0x81000000 0x3 0 1 0>; >> >> > bus-range = <0x00 0xff>; >> >> > - interrupt-map-mask = <0 0 0 0>; >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; >> >> > + interrupt-map-mask = <0 0 0 7>; >> >> > + interrupt-map = <0 0 0 1 &pcie3_intc 0>, >> >> > + <0 0 0 2 &pcie3_intc 1>, >> >> > + <0 0 0 3 &pcie3_intc 2>, >> >> > + <0 0 0 4 &pcie3_intc 3>; >> >> > marvell,pcie-port = <2>; >> >> > marvell,pcie-lane = <0>; >> >> > clocks = <&gateclk 6>; >> >> > status = "disabled"; >> >> > + pcie3_intc: interrupt-controller { >> >> > + interrupt-controller; >> >> > + #interrupt-cells = <1>; >> >> > + }; >> >> > }; >> >> > >> >> > /* >> >> > @@ -129,16 +156,25 @@ >> >> > reg = <0x2000 0 0 0 0>; >> >> > #address-cells = <3>; >> >> > #size-cells = <2>; >> >> > + interrupt-names = "intx"; >> >> > + interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; >> >> > #interrupt-cells = <1>; >> >> > ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 >> >> > 0x81000000 0 0 0x81000000 0x4 0 1 0>; >> >> > bus-range = <0x00 0xff>; >> >> > - interrupt-map-mask = <0 0 0 0>; >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; >> >> > + interrupt-map-mask = <0 0 0 7>; >> >> > + interrupt-map = <0 0 0 1 &pcie4_intc 0>, >> >> > + <0 0 0 2 &pcie4_intc 1>, >> >> > + <0 0 0 3 &pcie4_intc 2>, >> >> > + <0 0 0 4 &pcie4_intc 3>; >> >> > marvell,pcie-port = <3>; >> >> > marvell,pcie-lane = <0>; >> >> > clocks = <&gateclk 7>; >> >> > status = "disabled"; >> >> > + pcie4_intc: interrupt-controller { >> >> > + interrupt-controller; >> >> > + #interrupt-cells = <1>; >> >> > + }; >> >> > }; >> >> > }; >> >> > }; >> >> > -- >> >> > 2.20.1 >> >> > >> >> >> >> -- >> >> Gregory Clement, Bootlin >> >> Embedded Linux and Kernel engineering >> >> http://bootlin.com >> >> -- >> Gregory Clement, Bootlin >> Embedded Linux and Kernel engineering >> http://bootlin.com
Hello! armada-388.dtsi file has #include "armada-385.dtsi" line and therefore is already covered by this my patch. Gregory's question was about A380. But if you want, you can test this patch series (which already covers A388) on your A388 HW. It is still better to do tests on more HW. On Tuesday 15 February 2022 10:48:17 Luís Mendes wrote: > Hello, > > Sorry for jumping in the conversation, but I read this thread and I > have an Armada A388 HW so I can test it, if desired. > > Luís > > > On Tue, Feb 15, 2022 at 10:47 AM Luís Mendes <luis.p.mendes@gmail.com> wrote: > > > > Hello, > > > > Sorry for jumping in the conversation, but I read this thread and I have an Armada A388 HW so I can test it, if desired. > > > > Luís > > > > On Mon, Feb 14, 2022 at 7:57 PM Gregory CLEMENT <gregory.clement@bootlin.com> wrote: > >> > >> Hello, > >> > >> > On Monday 14 February 2022 16:07:13 Gregory CLEMENT wrote: > >> >> Hello Pali, > >> >> > >> >> > With this change legacy INTA, INTB, INTC and INTD interrupts are reported > >> >> > separately and not mixed into one Linux virq source anymore. > >> >> > > >> >> > Signed-off-by: Pali Rohár <pali@kernel.org> > >> >> > --- > >> >> > arch/arm/boot/dts/armada-385.dtsi | 52 ++++++++++++++++++++++++++----- > >> >> > >> >> Is there any reason for not doing the same change in armada-380.dtsi ? > >> > > >> > I do not have A380 HW, so I did this change only for A385 which I have > >> > tested. > >> > >> OK fair enough. > >> > >> So you can add my > >> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> > >> > >> Moreover to keep biscetability this patch should be merged after the > >> support in the driver. So the easier is to let merge it through the PCI > >> subsystem with the other patches from this series. I do not think there > >> will be any other changes in this file so there won't be any merge > >> conflicts. > >> > >> Thanks, > >> > >> Grégory > >> > >> > >> > > >> >> Grégory > >> >> > >> >> > 1 file changed, 44 insertions(+), 8 deletions(-) > >> >> > > >> >> > diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi > >> >> > index f0022d10c715..83392b92dae2 100644 > >> >> > --- a/arch/arm/boot/dts/armada-385.dtsi > >> >> > +++ b/arch/arm/boot/dts/armada-385.dtsi > >> >> > @@ -69,16 +69,25 @@ > >> >> > reg = <0x0800 0 0 0 0>; > >> >> > #address-cells = <3>; > >> >> > #size-cells = <2>; > >> >> > + interrupt-names = "intx"; > >> >> > + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; > >> >> > #interrupt-cells = <1>; > >> >> > ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 > >> >> > 0x81000000 0 0 0x81000000 0x1 0 1 0>; > >> >> > bus-range = <0x00 0xff>; > >> >> > - interrupt-map-mask = <0 0 0 0>; > >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; > >> >> > + interrupt-map-mask = <0 0 0 7>; > >> >> > + interrupt-map = <0 0 0 1 &pcie1_intc 0>, > >> >> > + <0 0 0 2 &pcie1_intc 1>, > >> >> > + <0 0 0 3 &pcie1_intc 2>, > >> >> > + <0 0 0 4 &pcie1_intc 3>; > >> >> > marvell,pcie-port = <0>; > >> >> > marvell,pcie-lane = <0>; > >> >> > clocks = <&gateclk 8>; > >> >> > status = "disabled"; > >> >> > + pcie1_intc: interrupt-controller { > >> >> > + interrupt-controller; > >> >> > + #interrupt-cells = <1>; > >> >> > + }; > >> >> > }; > >> >> > > >> >> > /* x1 port */ > >> >> > @@ -88,16 +97,25 @@ > >> >> > reg = <0x1000 0 0 0 0>; > >> >> > #address-cells = <3>; > >> >> > #size-cells = <2>; > >> >> > + interrupt-names = "intx"; > >> >> > + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > >> >> > #interrupt-cells = <1>; > >> >> > ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 > >> >> > 0x81000000 0 0 0x81000000 0x2 0 1 0>; > >> >> > bus-range = <0x00 0xff>; > >> >> > - interrupt-map-mask = <0 0 0 0>; > >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > >> >> > + interrupt-map-mask = <0 0 0 7>; > >> >> > + interrupt-map = <0 0 0 1 &pcie2_intc 0>, > >> >> > + <0 0 0 2 &pcie2_intc 1>, > >> >> > + <0 0 0 3 &pcie2_intc 2>, > >> >> > + <0 0 0 4 &pcie2_intc 3>; > >> >> > marvell,pcie-port = <1>; > >> >> > marvell,pcie-lane = <0>; > >> >> > clocks = <&gateclk 5>; > >> >> > status = "disabled"; > >> >> > + pcie2_intc: interrupt-controller { > >> >> > + interrupt-controller; > >> >> > + #interrupt-cells = <1>; > >> >> > + }; > >> >> > }; > >> >> > > >> >> > /* x1 port */ > >> >> > @@ -107,16 +125,25 @@ > >> >> > reg = <0x1800 0 0 0 0>; > >> >> > #address-cells = <3>; > >> >> > #size-cells = <2>; > >> >> > + interrupt-names = "intx"; > >> >> > + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > >> >> > #interrupt-cells = <1>; > >> >> > ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 > >> >> > 0x81000000 0 0 0x81000000 0x3 0 1 0>; > >> >> > bus-range = <0x00 0xff>; > >> >> > - interrupt-map-mask = <0 0 0 0>; > >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > >> >> > + interrupt-map-mask = <0 0 0 7>; > >> >> > + interrupt-map = <0 0 0 1 &pcie3_intc 0>, > >> >> > + <0 0 0 2 &pcie3_intc 1>, > >> >> > + <0 0 0 3 &pcie3_intc 2>, > >> >> > + <0 0 0 4 &pcie3_intc 3>; > >> >> > marvell,pcie-port = <2>; > >> >> > marvell,pcie-lane = <0>; > >> >> > clocks = <&gateclk 6>; > >> >> > status = "disabled"; > >> >> > + pcie3_intc: interrupt-controller { > >> >> > + interrupt-controller; > >> >> > + #interrupt-cells = <1>; > >> >> > + }; > >> >> > }; > >> >> > > >> >> > /* > >> >> > @@ -129,16 +156,25 @@ > >> >> > reg = <0x2000 0 0 0 0>; > >> >> > #address-cells = <3>; > >> >> > #size-cells = <2>; > >> >> > + interrupt-names = "intx"; > >> >> > + interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > >> >> > #interrupt-cells = <1>; > >> >> > ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 > >> >> > 0x81000000 0 0 0x81000000 0x4 0 1 0>; > >> >> > bus-range = <0x00 0xff>; > >> >> > - interrupt-map-mask = <0 0 0 0>; > >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > >> >> > + interrupt-map-mask = <0 0 0 7>; > >> >> > + interrupt-map = <0 0 0 1 &pcie4_intc 0>, > >> >> > + <0 0 0 2 &pcie4_intc 1>, > >> >> > + <0 0 0 3 &pcie4_intc 2>, > >> >> > + <0 0 0 4 &pcie4_intc 3>; > >> >> > marvell,pcie-port = <3>; > >> >> > marvell,pcie-lane = <0>; > >> >> > clocks = <&gateclk 7>; > >> >> > status = "disabled"; > >> >> > + pcie4_intc: interrupt-controller { > >> >> > + interrupt-controller; > >> >> > + #interrupt-cells = <1>; > >> >> > + }; > >> >> > }; > >> >> > }; > >> >> > }; > >> >> > -- > >> >> > 2.20.1 > >> >> > > >> >> > >> >> -- > >> >> Gregory Clement, Bootlin > >> >> Embedded Linux and Kernel engineering > >> >> http://bootlin.com > >> > >> -- > >> Gregory Clement, Bootlin > >> Embedded Linux and Kernel engineering > >> http://bootlin.com
Successfully tested on my custom A388 system with two PCI express slots. If you wish you can add a: Tested-by: Luis Mendes <luis.p.mendes@gmail.com> On Tue, Feb 15, 2022 at 10:52 AM Pali Rohár <pali@kernel.org> wrote: > > Hello! armada-388.dtsi file has #include "armada-385.dtsi" line and > therefore is already covered by this my patch. > > Gregory's question was about A380. > > But if you want, you can test this patch series (which already covers > A388) on your A388 HW. It is still better to do tests on more HW. > > On Tuesday 15 February 2022 10:48:17 Luís Mendes wrote: > > Hello, > > > > Sorry for jumping in the conversation, but I read this thread and I > > have an Armada A388 HW so I can test it, if desired. > > > > Luís > > > > > > On Tue, Feb 15, 2022 at 10:47 AM Luís Mendes <luis.p.mendes@gmail.com> wrote: > > > > > > Hello, > > > > > > Sorry for jumping in the conversation, but I read this thread and I have an Armada A388 HW so I can test it, if desired. > > > > > > Luís > > > > > > On Mon, Feb 14, 2022 at 7:57 PM Gregory CLEMENT <gregory.clement@bootlin.com> wrote: > > >> > > >> Hello, > > >> > > >> > On Monday 14 February 2022 16:07:13 Gregory CLEMENT wrote: > > >> >> Hello Pali, > > >> >> > > >> >> > With this change legacy INTA, INTB, INTC and INTD interrupts are reported > > >> >> > separately and not mixed into one Linux virq source anymore. > > >> >> > > > >> >> > Signed-off-by: Pali Rohár <pali@kernel.org> > > >> >> > --- > > >> >> > arch/arm/boot/dts/armada-385.dtsi | 52 ++++++++++++++++++++++++++----- > > >> >> > > >> >> Is there any reason for not doing the same change in armada-380.dtsi ? > > >> > > > >> > I do not have A380 HW, so I did this change only for A385 which I have > > >> > tested. > > >> > > >> OK fair enough. > > >> > > >> So you can add my > > >> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> > > >> > > >> Moreover to keep biscetability this patch should be merged after the > > >> support in the driver. So the easier is to let merge it through the PCI > > >> subsystem with the other patches from this series. I do not think there > > >> will be any other changes in this file so there won't be any merge > > >> conflicts. > > >> > > >> Thanks, > > >> > > >> Grégory > > >> > > >> > > >> > > > >> >> Grégory > > >> >> > > >> >> > 1 file changed, 44 insertions(+), 8 deletions(-) > > >> >> > > > >> >> > diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi > > >> >> > index f0022d10c715..83392b92dae2 100644 > > >> >> > --- a/arch/arm/boot/dts/armada-385.dtsi > > >> >> > +++ b/arch/arm/boot/dts/armada-385.dtsi > > >> >> > @@ -69,16 +69,25 @@ > > >> >> > reg = <0x0800 0 0 0 0>; > > >> >> > #address-cells = <3>; > > >> >> > #size-cells = <2>; > > >> >> > + interrupt-names = "intx"; > > >> >> > + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; > > >> >> > #interrupt-cells = <1>; > > >> >> > ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 > > >> >> > 0x81000000 0 0 0x81000000 0x1 0 1 0>; > > >> >> > bus-range = <0x00 0xff>; > > >> >> > - interrupt-map-mask = <0 0 0 0>; > > >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; > > >> >> > + interrupt-map-mask = <0 0 0 7>; > > >> >> > + interrupt-map = <0 0 0 1 &pcie1_intc 0>, > > >> >> > + <0 0 0 2 &pcie1_intc 1>, > > >> >> > + <0 0 0 3 &pcie1_intc 2>, > > >> >> > + <0 0 0 4 &pcie1_intc 3>; > > >> >> > marvell,pcie-port = <0>; > > >> >> > marvell,pcie-lane = <0>; > > >> >> > clocks = <&gateclk 8>; > > >> >> > status = "disabled"; > > >> >> > + pcie1_intc: interrupt-controller { > > >> >> > + interrupt-controller; > > >> >> > + #interrupt-cells = <1>; > > >> >> > + }; > > >> >> > }; > > >> >> > > > >> >> > /* x1 port */ > > >> >> > @@ -88,16 +97,25 @@ > > >> >> > reg = <0x1000 0 0 0 0>; > > >> >> > #address-cells = <3>; > > >> >> > #size-cells = <2>; > > >> >> > + interrupt-names = "intx"; > > >> >> > + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > > >> >> > #interrupt-cells = <1>; > > >> >> > ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 > > >> >> > 0x81000000 0 0 0x81000000 0x2 0 1 0>; > > >> >> > bus-range = <0x00 0xff>; > > >> >> > - interrupt-map-mask = <0 0 0 0>; > > >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > > >> >> > + interrupt-map-mask = <0 0 0 7>; > > >> >> > + interrupt-map = <0 0 0 1 &pcie2_intc 0>, > > >> >> > + <0 0 0 2 &pcie2_intc 1>, > > >> >> > + <0 0 0 3 &pcie2_intc 2>, > > >> >> > + <0 0 0 4 &pcie2_intc 3>; > > >> >> > marvell,pcie-port = <1>; > > >> >> > marvell,pcie-lane = <0>; > > >> >> > clocks = <&gateclk 5>; > > >> >> > status = "disabled"; > > >> >> > + pcie2_intc: interrupt-controller { > > >> >> > + interrupt-controller; > > >> >> > + #interrupt-cells = <1>; > > >> >> > + }; > > >> >> > }; > > >> >> > > > >> >> > /* x1 port */ > > >> >> > @@ -107,16 +125,25 @@ > > >> >> > reg = <0x1800 0 0 0 0>; > > >> >> > #address-cells = <3>; > > >> >> > #size-cells = <2>; > > >> >> > + interrupt-names = "intx"; > > >> >> > + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > > >> >> > #interrupt-cells = <1>; > > >> >> > ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 > > >> >> > 0x81000000 0 0 0x81000000 0x3 0 1 0>; > > >> >> > bus-range = <0x00 0xff>; > > >> >> > - interrupt-map-mask = <0 0 0 0>; > > >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > > >> >> > + interrupt-map-mask = <0 0 0 7>; > > >> >> > + interrupt-map = <0 0 0 1 &pcie3_intc 0>, > > >> >> > + <0 0 0 2 &pcie3_intc 1>, > > >> >> > + <0 0 0 3 &pcie3_intc 2>, > > >> >> > + <0 0 0 4 &pcie3_intc 3>; > > >> >> > marvell,pcie-port = <2>; > > >> >> > marvell,pcie-lane = <0>; > > >> >> > clocks = <&gateclk 6>; > > >> >> > status = "disabled"; > > >> >> > + pcie3_intc: interrupt-controller { > > >> >> > + interrupt-controller; > > >> >> > + #interrupt-cells = <1>; > > >> >> > + }; > > >> >> > }; > > >> >> > > > >> >> > /* > > >> >> > @@ -129,16 +156,25 @@ > > >> >> > reg = <0x2000 0 0 0 0>; > > >> >> > #address-cells = <3>; > > >> >> > #size-cells = <2>; > > >> >> > + interrupt-names = "intx"; > > >> >> > + interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > > >> >> > #interrupt-cells = <1>; > > >> >> > ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 > > >> >> > 0x81000000 0 0 0x81000000 0x4 0 1 0>; > > >> >> > bus-range = <0x00 0xff>; > > >> >> > - interrupt-map-mask = <0 0 0 0>; > > >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > > >> >> > + interrupt-map-mask = <0 0 0 7>; > > >> >> > + interrupt-map = <0 0 0 1 &pcie4_intc 0>, > > >> >> > + <0 0 0 2 &pcie4_intc 1>, > > >> >> > + <0 0 0 3 &pcie4_intc 2>, > > >> >> > + <0 0 0 4 &pcie4_intc 3>; > > >> >> > marvell,pcie-port = <3>; > > >> >> > marvell,pcie-lane = <0>; > > >> >> > clocks = <&gateclk 7>; > > >> >> > status = "disabled"; > > >> >> > + pcie4_intc: interrupt-controller { > > >> >> > + interrupt-controller; > > >> >> > + #interrupt-cells = <1>; > > >> >> > + }; > > >> >> > }; > > >> >> > }; > > >> >> > }; > > >> >> > -- > > >> >> > 2.20.1 > > >> >> > > > >> >> > > >> >> -- > > >> >> Gregory Clement, Bootlin > > >> >> Embedded Linux and Kernel engineering > > >> >> http://bootlin.com > > >> > > >> -- > > >> Gregory Clement, Bootlin > > >> Embedded Linux and Kernel engineering > > >> http://bootlin.com
Perfect, thanks! On Friday 18 February 2022 21:53:43 Luís Mendes wrote: > Successfully tested on my custom A388 system with two PCI express slots. > > If you wish you can add a: > Tested-by: Luis Mendes <luis.p.mendes@gmail.com> > > On Tue, Feb 15, 2022 at 10:52 AM Pali Rohár <pali@kernel.org> wrote: > > > > Hello! armada-388.dtsi file has #include "armada-385.dtsi" line and > > therefore is already covered by this my patch. > > > > Gregory's question was about A380. > > > > But if you want, you can test this patch series (which already covers > > A388) on your A388 HW. It is still better to do tests on more HW. > > > > On Tuesday 15 February 2022 10:48:17 Luís Mendes wrote: > > > Hello, > > > > > > Sorry for jumping in the conversation, but I read this thread and I > > > have an Armada A388 HW so I can test it, if desired. > > > > > > Luís > > > > > > > > > On Tue, Feb 15, 2022 at 10:47 AM Luís Mendes <luis.p.mendes@gmail.com> wrote: > > > > > > > > Hello, > > > > > > > > Sorry for jumping in the conversation, but I read this thread and I have an Armada A388 HW so I can test it, if desired. > > > > > > > > Luís > > > > > > > > On Mon, Feb 14, 2022 at 7:57 PM Gregory CLEMENT <gregory.clement@bootlin.com> wrote: > > > >> > > > >> Hello, > > > >> > > > >> > On Monday 14 February 2022 16:07:13 Gregory CLEMENT wrote: > > > >> >> Hello Pali, > > > >> >> > > > >> >> > With this change legacy INTA, INTB, INTC and INTD interrupts are reported > > > >> >> > separately and not mixed into one Linux virq source anymore. > > > >> >> > > > > >> >> > Signed-off-by: Pali Rohár <pali@kernel.org> > > > >> >> > --- > > > >> >> > arch/arm/boot/dts/armada-385.dtsi | 52 ++++++++++++++++++++++++++----- > > > >> >> > > > >> >> Is there any reason for not doing the same change in armada-380.dtsi ? > > > >> > > > > >> > I do not have A380 HW, so I did this change only for A385 which I have > > > >> > tested. > > > >> > > > >> OK fair enough. > > > >> > > > >> So you can add my > > > >> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> > > > >> > > > >> Moreover to keep biscetability this patch should be merged after the > > > >> support in the driver. So the easier is to let merge it through the PCI > > > >> subsystem with the other patches from this series. I do not think there > > > >> will be any other changes in this file so there won't be any merge > > > >> conflicts. > > > >> > > > >> Thanks, > > > >> > > > >> Grégory > > > >> > > > >> > > > >> > > > > >> >> Grégory > > > >> >> > > > >> >> > 1 file changed, 44 insertions(+), 8 deletions(-) > > > >> >> > > > > >> >> > diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi > > > >> >> > index f0022d10c715..83392b92dae2 100644 > > > >> >> > --- a/arch/arm/boot/dts/armada-385.dtsi > > > >> >> > +++ b/arch/arm/boot/dts/armada-385.dtsi > > > >> >> > @@ -69,16 +69,25 @@ > > > >> >> > reg = <0x0800 0 0 0 0>; > > > >> >> > #address-cells = <3>; > > > >> >> > #size-cells = <2>; > > > >> >> > + interrupt-names = "intx"; > > > >> >> > + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; > > > >> >> > #interrupt-cells = <1>; > > > >> >> > ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 > > > >> >> > 0x81000000 0 0 0x81000000 0x1 0 1 0>; > > > >> >> > bus-range = <0x00 0xff>; > > > >> >> > - interrupt-map-mask = <0 0 0 0>; > > > >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; > > > >> >> > + interrupt-map-mask = <0 0 0 7>; > > > >> >> > + interrupt-map = <0 0 0 1 &pcie1_intc 0>, > > > >> >> > + <0 0 0 2 &pcie1_intc 1>, > > > >> >> > + <0 0 0 3 &pcie1_intc 2>, > > > >> >> > + <0 0 0 4 &pcie1_intc 3>; > > > >> >> > marvell,pcie-port = <0>; > > > >> >> > marvell,pcie-lane = <0>; > > > >> >> > clocks = <&gateclk 8>; > > > >> >> > status = "disabled"; > > > >> >> > + pcie1_intc: interrupt-controller { > > > >> >> > + interrupt-controller; > > > >> >> > + #interrupt-cells = <1>; > > > >> >> > + }; > > > >> >> > }; > > > >> >> > > > > >> >> > /* x1 port */ > > > >> >> > @@ -88,16 +97,25 @@ > > > >> >> > reg = <0x1000 0 0 0 0>; > > > >> >> > #address-cells = <3>; > > > >> >> > #size-cells = <2>; > > > >> >> > + interrupt-names = "intx"; > > > >> >> > + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > > > >> >> > #interrupt-cells = <1>; > > > >> >> > ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 > > > >> >> > 0x81000000 0 0 0x81000000 0x2 0 1 0>; > > > >> >> > bus-range = <0x00 0xff>; > > > >> >> > - interrupt-map-mask = <0 0 0 0>; > > > >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > > > >> >> > + interrupt-map-mask = <0 0 0 7>; > > > >> >> > + interrupt-map = <0 0 0 1 &pcie2_intc 0>, > > > >> >> > + <0 0 0 2 &pcie2_intc 1>, > > > >> >> > + <0 0 0 3 &pcie2_intc 2>, > > > >> >> > + <0 0 0 4 &pcie2_intc 3>; > > > >> >> > marvell,pcie-port = <1>; > > > >> >> > marvell,pcie-lane = <0>; > > > >> >> > clocks = <&gateclk 5>; > > > >> >> > status = "disabled"; > > > >> >> > + pcie2_intc: interrupt-controller { > > > >> >> > + interrupt-controller; > > > >> >> > + #interrupt-cells = <1>; > > > >> >> > + }; > > > >> >> > }; > > > >> >> > > > > >> >> > /* x1 port */ > > > >> >> > @@ -107,16 +125,25 @@ > > > >> >> > reg = <0x1800 0 0 0 0>; > > > >> >> > #address-cells = <3>; > > > >> >> > #size-cells = <2>; > > > >> >> > + interrupt-names = "intx"; > > > >> >> > + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > > > >> >> > #interrupt-cells = <1>; > > > >> >> > ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 > > > >> >> > 0x81000000 0 0 0x81000000 0x3 0 1 0>; > > > >> >> > bus-range = <0x00 0xff>; > > > >> >> > - interrupt-map-mask = <0 0 0 0>; > > > >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > > > >> >> > + interrupt-map-mask = <0 0 0 7>; > > > >> >> > + interrupt-map = <0 0 0 1 &pcie3_intc 0>, > > > >> >> > + <0 0 0 2 &pcie3_intc 1>, > > > >> >> > + <0 0 0 3 &pcie3_intc 2>, > > > >> >> > + <0 0 0 4 &pcie3_intc 3>; > > > >> >> > marvell,pcie-port = <2>; > > > >> >> > marvell,pcie-lane = <0>; > > > >> >> > clocks = <&gateclk 6>; > > > >> >> > status = "disabled"; > > > >> >> > + pcie3_intc: interrupt-controller { > > > >> >> > + interrupt-controller; > > > >> >> > + #interrupt-cells = <1>; > > > >> >> > + }; > > > >> >> > }; > > > >> >> > > > > >> >> > /* > > > >> >> > @@ -129,16 +156,25 @@ > > > >> >> > reg = <0x2000 0 0 0 0>; > > > >> >> > #address-cells = <3>; > > > >> >> > #size-cells = <2>; > > > >> >> > + interrupt-names = "intx"; > > > >> >> > + interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > > > >> >> > #interrupt-cells = <1>; > > > >> >> > ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 > > > >> >> > 0x81000000 0 0 0x81000000 0x4 0 1 0>; > > > >> >> > bus-range = <0x00 0xff>; > > > >> >> > - interrupt-map-mask = <0 0 0 0>; > > > >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > > > >> >> > + interrupt-map-mask = <0 0 0 7>; > > > >> >> > + interrupt-map = <0 0 0 1 &pcie4_intc 0>, > > > >> >> > + <0 0 0 2 &pcie4_intc 1>, > > > >> >> > + <0 0 0 3 &pcie4_intc 2>, > > > >> >> > + <0 0 0 4 &pcie4_intc 3>; > > > >> >> > marvell,pcie-port = <3>; > > > >> >> > marvell,pcie-lane = <0>; > > > >> >> > clocks = <&gateclk 7>; > > > >> >> > status = "disabled"; > > > >> >> > + pcie4_intc: interrupt-controller { > > > >> >> > + interrupt-controller; > > > >> >> > + #interrupt-cells = <1>; > > > >> >> > + }; > > > >> >> > }; > > > >> >> > }; > > > >> >> > }; > > > >> >> > -- > > > >> >> > 2.20.1 > > > >> >> > > > > >> >> > > > >> >> -- > > > >> >> Gregory Clement, Bootlin > > > >> >> Embedded Linux and Kernel engineering > > > >> >> http://bootlin.com > > > >> > > > >> -- > > > >> Gregory Clement, Bootlin > > > >> Embedded Linux and Kernel engineering > > > >> http://bootlin.com
diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi index f0022d10c715..83392b92dae2 100644 --- a/arch/arm/boot/dts/armada-385.dtsi +++ b/arch/arm/boot/dts/armada-385.dtsi @@ -69,16 +69,25 @@ reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 8>; status = "disabled"; + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* x1 port */ @@ -88,16 +97,25 @@ reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; status = "disabled"; + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* x1 port */ @@ -107,16 +125,25 @@ reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; marvell,pcie-port = <2>; marvell,pcie-lane = <0>; clocks = <&gateclk 6>; status = "disabled"; + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* @@ -129,16 +156,25 @@ reg = <0x2000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie4_intc 0>, + <0 0 0 2 &pcie4_intc 1>, + <0 0 0 3 &pcie4_intc 2>, + <0 0 0 4 &pcie4_intc 3>; marvell,pcie-port = <3>; marvell,pcie-lane = <0>; clocks = <&gateclk 7>; status = "disabled"; + pcie4_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; };
With this change legacy INTA, INTB, INTC and INTD interrupts are reported separately and not mixed into one Linux virq source anymore. Signed-off-by: Pali Rohár <pali@kernel.org> --- arch/arm/boot/dts/armada-385.dtsi | 52 ++++++++++++++++++++++++++----- 1 file changed, 44 insertions(+), 8 deletions(-)