From patchwork Wed Jan 12 17:33:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TcOlbnMgUnVsbGfDpXJk?= X-Patchwork-Id: 12711666 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 77CECC433EF for ; Wed, 12 Jan 2022 17:35:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=5xtWj8uTEjL6vfSzzap553GfU3JH1tIDgDEtfcJ+Oto=; b=nxX2rxEI9C3MNg VjZv65J0A3ZaNyQrhjYTGjhNMROW7NRqAh87AqBenLfWxD/+dgEiNhSjxP22aHsr7srPjArHd3hJw XAl+PY7JzL+YM0tGNwKmLXMKq8fcwl/S+rfvUQ5lTQOjI6L1y7WPRz3qtDC4i8YK2OsYCGeX+Oj+y QBcpuAy9JmPoCe3A9I6yxCjhQ676feX3wlDGRYz2HvlDAVOuBtC9O1+B1KeaX1OBUJSM+jomdZhOG 39LQjvVEi2QFyzIu1AtqZAsKR0AuzrC7x7aQS6KCU+L6BYBbUIxLM41qNLKPS+e+cLUCAA63lHrVf edvxb+D2Hy+g7ibBBl1Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n7hVc-003H06-Vm; Wed, 12 Jan 2022 17:34:05 +0000 Received: from unicorn.mansr.com ([81.2.72.234]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n7hVZ-003GxU-Nh for linux-arm-kernel@lists.infradead.org; Wed, 12 Jan 2022 17:34:03 +0000 Received: from raven.mansr.com (raven.mansr.com [81.2.72.235]) by unicorn.mansr.com (Postfix) with ESMTPS id B616715360; Wed, 12 Jan 2022 17:33:55 +0000 (GMT) Received: by raven.mansr.com (Postfix, from userid 51770) id 8F365219FD4; Wed, 12 Jan 2022 17:33:55 +0000 (GMT) From: Mans Rullgard To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] ARM: dts: sunxi: h3/h5: add r_uart node Date: Wed, 12 Jan 2022 17:33:27 +0000 Message-Id: <20220112173327.26317-1-mans@mansr.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220112_093401_939962_0DFB8109 X-CRM114-Status: UNSURE ( 9.73 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org There is an additional UART in the PL I/O block. Add a node and pinmux for it. Signed-off-by: Mans Rullgard --- The "documentation" doesn't mention any DMA channels for this UART. If it nonetheless does have DMA capability and someone knows the channel assignments, feel free to amend. --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 22d533d18992..55ffba5a4e9f 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -884,6 +884,19 @@ r_i2c: i2c@1f02400 { #size-cells = <0>; }; + r_uart: serial@1f02800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01f02800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&r_ccu CLK_APB0_UART>; + resets = <&r_ccu RST_APB0_UART>; + pinctrl-names = "default"; + pinctrl-0 = <&r_uart_pins>; + status = "disabled"; + }; + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun8i-h3-r-pinctrl"; reg = <0x01f02c00 0x400>; @@ -909,6 +922,11 @@ r_pwm_pin: r-pwm-pin { pins = "PL10"; function = "s_pwm"; }; + + r_uart_pins: r-uart-pins { + pins = "PL2", "PL3"; + function = "s_uart"; + }; }; r_pwm: pwm@1f03800 {