From patchwork Thu Jan 13 06:58:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 12712334 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4BA0FC433F5 for ; Thu, 13 Jan 2022 07:02:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TBR96ZhMwHpMr/Swb8dB+EFyBb9tfrMby6o9+ZVZEEE=; b=hrLKdqOnIpoedw iaarXjhj5FnASkCGV9KDN/Tm7p6J6Y9CJbOInqIO+91o6aUB8H0JTIStIMA0Ktaz6gL6L0jK3qQMo fDE34hpF6wxFpx+h6C/FX79QgXRHgrGQmAvUDYs3tGOQPEUbcRfuR0FgHDjVxK93gbofJ2m6bd6ru fDg7Yv6sEWzz9i1qJHAKP/dAxYN52TJkC9F6IzPMFsBvpzovewtiTcFHYCkxnGS0tX8Od7XJgkntK zXVnGsdyXQPBHvm5aX6wdq9gBI1BzBX2+iWg9W20TPHDYvH7shbCN/XQ+/J1mozm+/dJ+tgXODYj8 1/DgD922iIjd1Q8pzw2Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n7u6x-004uGq-Qh; Thu, 13 Jan 2022 07:01:27 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n7u6T-004u4h-F2; Thu, 13 Jan 2022 07:00:58 +0000 X-UUID: 1b7e824c566a4f699dfd46ee5cdd0c64-20220113 X-UUID: 1b7e824c566a4f699dfd46ee5cdd0c64-20220113 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 10674215; Thu, 13 Jan 2022 00:00:52 -0700 Received: from mtkmbs10n1.mediatek.inc (172.21.101.34) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 12 Jan 2022 22:58:27 -0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 13 Jan 2022 14:58:25 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 13 Jan 2022 14:58:24 +0800 From: allen-kh.cheng To: Matthias Brugger , Rob Herring , CC: , , , , , , , , Chen-Yu Tsai , Ryder Lee , Allen-KH Cheng Subject: [PATCH v4 2/5] arm64: dts: mediatek: Correct SPI clock of MT8192 Date: Thu, 13 Jan 2022 14:58:19 +0800 Message-ID: <20220113065822.11809-3-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220113065822.11809-1-allen-kh.cheng@mediatek.com> References: <20220113065822.11809-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220112_230057_529260_3B5D66D4 X-CRM114-Status: GOOD ( 11.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Allen-KH Cheng When the initial devicetree for mt8192 was added in 48489980e27e ("arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile"), the clock driver for mt8192 was not yet upstream, so the clock property nodes were set to the clk26m clock as a placeholder. Given that the clock driver has since been added through 710573dee31b ("clk: mediatek: Add MT8192 basic clocks support"), as well as its dt-bindings through f35f1a23e0e1 ("clk: mediatek: Add dt-bindings of MT8192 clocks") and devicetree nodes through 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 clock controllers"), fix the SPI clock property to point to the actual clock. Signed-off-by: Allen-KH Cheng Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 48 ++++++++++++------------ 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index cfb67cc40c2c..47d056cc5dad 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -355,9 +355,9 @@ #size-cells = <0>; reg = <0 0x1100a000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI0>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; @@ -369,9 +369,9 @@ #size-cells = <0>; reg = <0 0x11010000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI1>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; @@ -383,9 +383,9 @@ #size-cells = <0>; reg = <0 0x11012000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI2>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; @@ -397,9 +397,9 @@ #size-cells = <0>; reg = <0 0x11013000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI3>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; @@ -411,9 +411,9 @@ #size-cells = <0>; reg = <0 0x11018000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI4>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; @@ -425,9 +425,9 @@ #size-cells = <0>; reg = <0 0x11019000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI5>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; @@ -439,9 +439,9 @@ #size-cells = <0>; reg = <0 0x1101d000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI6>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; @@ -453,9 +453,9 @@ #size-cells = <0>; reg = <0 0x1101e000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI7>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; };