From patchwork Thu Jan 13 17:54:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: German Gomez X-Patchwork-Id: 12713024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E05FDC433F5 for ; Thu, 13 Jan 2022 17:56:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+7kQ1y29dIZtmjFusifbUpxABgg0z/KVk2GHgXytBX4=; b=aNfa1oSxZZz6VB S/Jkagal68slemq9Yaw1yAjDTG8VfSmjl572NOII5Pq8m1nT9k1tYNK0580XFrCZa+lxWaXqLsvTJ BxoQe7bvJ/n9Vcj59rGzkie/OK7SiUkgDqwMRJe6UruQnG0mMY/VjGUP0MegeRgFStPNaqgLy+XJ/ 307a0nKXwbF8Xb6IdKtdwSFn+QD+UgOdMGNbbRbpuYCH3mWyLQgNblRFwUOWWBF44m+9q+WOClI3S nmxh9PVqt9fkTrzO47bYfmO5+t2+P05vWfFKFbOYL/SHwm9koYPG7Rjj7FDYbQTrBKEvUWgGPb5VA tD87AumhxhA10EvkSI6w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n84JN-006nuW-B8; Thu, 13 Jan 2022 17:54:57 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n84JA-006nsA-MN for linux-arm-kernel@lists.infradead.org; Thu, 13 Jan 2022 17:54:46 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 756A2106F; Thu, 13 Jan 2022 09:54:43 -0800 (PST) Received: from ip-10-252-15-108.eu-west-1.compute.internal (unknown [10.252.15.108]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 698D73F766; Thu, 13 Jan 2022 09:54:42 -0800 (PST) From: German Gomez To: linux-eng@arm.com Cc: james.clark@arm.com, German Gomez , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] perf: arm_spe: make the PMSCR CX bit[3] consistent across the session Date: Thu, 13 Jan 2022 17:54:16 +0000 Message-Id: <20220113175417.5523-2-german.gomez@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220113175417.5523-1-german.gomez@arm.com> References: <20220113175417.5523-1-german.gomez@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220113_095444_843028_16CF32F5 X-CRM114-Status: GOOD ( 13.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The ARM SPE driver will seenablet the CX bit in the PMSCR register if it detects that the profiler (perf tool) has enough capabilities during the initialization of the PMU event in the "arm_spe_pmu_event_init" callback: reg = arm_spe_event_to_pmscr(event); if (!perfmon_capable() && (reg & (BIT(SYS_PMSCR_EL1_PA_SHIFT) | BIT(SYS_PMSCR_EL1_CX_SHIFT) | BIT(SYS_PMSCR_EL1_PCT_SHIFT)))) return -EACCES; This implies that the CX bit should remain consistent across the entire duration of the session. However, the value of the bit is later being changed (from 0 to 1 and vice versa) in the "arm_spe_pmu_start" callback Consider this example: 1. Run a process in the background with privileges in CPU0 $ taskset --cpu-list 0 sudo dd if=/dev/random of=/dev/null & [3] 3806 2. Begin a perf session without privileges (we shouldn't see CONTEXT packets) $ perf record -e arm_spe_0// -C0 -- sleep 1 $ perf report -D | grep CONTEXT . 0000000e: 65 df 0e 00 00 CONTEXT 0xedf el2 . 0000004e: 65 df 0e 00 00 CONTEXT 0xedf el2 . 0000008e: 65 df 0e 00 00 CONTEXT 0xedf el2 [...] One way to fix this is by caching the value of the CX bit during the initialization of the PMU event, so that it remains consistent during the session. Signed-off-by: German Gomez --- drivers/perf/arm_spe_pmu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index d44bcc29d..8515bf85c 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -57,6 +57,7 @@ struct arm_spe_pmu { u16 pmsver; u16 min_period; u16 counter_sz; + bool pmscr_cx; #define SPE_PMU_FEAT_FILT_EVT (1UL << 0) #define SPE_PMU_FEAT_FILT_TYP (1UL << 1) @@ -260,6 +261,7 @@ static const struct attribute_group *arm_spe_pmu_attr_groups[] = { static u64 arm_spe_event_to_pmscr(struct perf_event *event) { struct perf_event_attr *attr = &event->attr; + struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu); u64 reg = 0; reg |= ATTR_CFG_GET_FLD(attr, ts_enable) << SYS_PMSCR_EL1_TS_SHIFT; @@ -272,7 +274,7 @@ static u64 arm_spe_event_to_pmscr(struct perf_event *event) if (!attr->exclude_kernel) reg |= BIT(SYS_PMSCR_EL1_E1SPE_SHIFT); - if (IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR) && perfmon_capable()) + if (IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR) && spe_pmu->pmscr_cx) reg |= BIT(SYS_PMSCR_EL1_CX_SHIFT); return reg; @@ -709,10 +711,10 @@ static int arm_spe_pmu_event_init(struct perf_event *event) !(spe_pmu->features & SPE_PMU_FEAT_FILT_LAT)) return -EOPNOTSUPP; + spe_pmu->pmscr_cx = perfmon_capable(); reg = arm_spe_event_to_pmscr(event); if (!perfmon_capable() && (reg & (BIT(SYS_PMSCR_EL1_PA_SHIFT) | - BIT(SYS_PMSCR_EL1_CX_SHIFT) | BIT(SYS_PMSCR_EL1_PCT_SHIFT)))) return -EACCES;