| Message ID | 20220114092110.12137-2-rex-bc.chen@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | force hsa hbp hfp packets multiple of lanenum to avoid screen shift | expand |
Il 14/01/22 10:21, Rex-BC Chen ha scritto: > Since a HS transmission is composed of an arbitrary number > of bytes that may not be an integer multiple of lanes, some > lanes may run out of data before others. > (Defined in 6.1.3 of mipi_DSI_specification_v.01-02-00) > > However, for some DSI RX devices (for example, anx7625), > there is a limitation that packet number should be the same > on all DSI lanes. In other words, they need to end a HS at > the same time. > > Because this limitation is for some specific DSI RX devices, > it is more reasonable to put the enable control in these > DSI RX drivers. If DSI TX driver knows the information, > they can adjust the setting for this situation. > > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > include/drm/drm_mipi_dsi.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h > index 147e51b6d241..342dfe5a0874 100644 > --- a/include/drm/drm_mipi_dsi.h > +++ b/include/drm/drm_mipi_dsi.h > @@ -137,6 +137,8 @@ struct mipi_dsi_host *of_find_mipi_dsi_host_by_node(struct device_node *node); > #define MIPI_DSI_CLOCK_NON_CONTINUOUS BIT(10) > /* transmit data in low power */ > #define MIPI_DSI_MODE_LPM BIT(11) > +/* transmit data ending in the same hsync for all lanes */ > +#define MIPI_DSI_HS_PKT_END_ALIGNED BIT(12) > > enum mipi_dsi_pixel_format { > MIPI_DSI_FMT_RGB888, >
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index 147e51b6d241..342dfe5a0874 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -137,6 +137,8 @@ struct mipi_dsi_host *of_find_mipi_dsi_host_by_node(struct device_node *node); #define MIPI_DSI_CLOCK_NON_CONTINUOUS BIT(10) /* transmit data in low power */ #define MIPI_DSI_MODE_LPM BIT(11) +/* transmit data ending in the same hsync for all lanes */ +#define MIPI_DSI_HS_PKT_END_ALIGNED BIT(12) enum mipi_dsi_pixel_format { MIPI_DSI_FMT_RGB888,