From patchwork Tue Jan 18 10:07:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jammy Huang X-Patchwork-Id: 12716130 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 19B9DC433EF for ; Tue, 18 Jan 2022 10:09:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Cc:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=bdnfeAJm0PINEfeRGIfr1lBTsjgKVD8ww07Xv6yZ/JE=; b=yxWvf0jKTKhi2P /r2DyM+1KZJoTFPAYX+sBl92IFHZvBp8OMkK01k5CNaNbDHTzyxXJ762oOdnarpJg1k4WDEnLlFB0 BMC5OG+yedXQgV6q8TdA+xa+rScGGL+WbJCKVRMiE4LUFIyhPPjVUOtbw6t44blWxlKXwXsdg0Ijq NTUI0Tw8+/7rBJdf/LpHjqMLNS8WQtk51X2NtRA3QTfe0ie6jV6DDWbVmE+beIZXhGV0P1guWlY4R Ly+n7YlZsuvnJAOvVpZInCSDDRRF7frLpftMPpxog2uHYzp/4JHLP5ida0fvX7+2uyrdantaepTUV BU93gQxZ+PPyr1W7HKkg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n9lPU-0015u6-O5; Tue, 18 Jan 2022 10:08:16 +0000 Received: from [211.20.114.71] (helo=twspam01.aspeedtech.com) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n9lP9-0015or-Jy for linux-arm-kernel@lists.infradead.org; Tue, 18 Jan 2022 10:07:57 +0000 Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 20IA0Rfm021057; Tue, 18 Jan 2022 18:00:27 +0800 (GMT-8) (envelope-from jammy_huang@aspeedtech.com) Received: from JammyHuang-PC.aspeed.com (192.168.2.115) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 18 Jan 2022 18:07:24 +0800 From: Jammy Huang To: , , , , , , , , Subject: [PATCH v4 1/2] media: aspeed: Add macro for the fields of the mode-detect registers Date: Tue, 18 Jan 2022 18:07:28 +0800 Message-ID: <20220118100729.7651-2-jammy_huang@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220118100729.7651-1-jammy_huang@aspeedtech.com> References: <20220118100729.7651-1-jammy_huang@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.2.115] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 20IA0Rfm021057 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220118_020755_930929_1020D24C X-CRM114-Status: UNSURE ( 9.63 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org VE_MODE_DT_HOR_TOLER: the tolerance in detecting for stable horizontal signal. VE_MODE_DT_VER_TOLER: the tolerance in detecting for stable vertical signal. VE_MODE_DT_HOR_STABLE: the minimum required count in detecting stable HSYNC signal to set mode detection horizontal signal stable. VE_MODE_DT_VER_STABLE: the minimum required count in detecting stable VSYNC signal to set mode detection vertical signal stable. Signed-off-by: Jammy Huang --- drivers/media/platform/aspeed-video.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/aspeed-video.c b/drivers/media/platform/aspeed-video.c index 4f5f5dd364ee..5ba4d70c8dab 100644 --- a/drivers/media/platform/aspeed-video.c +++ b/drivers/media/platform/aspeed-video.c @@ -190,6 +190,12 @@ #define VE_INTERRUPT_VSYNC_DESC BIT(11) #define VE_MODE_DETECT 0x30c +#define VE_MODE_DT_HOR_TOLER GENMASK(31, 28) +#define VE_MODE_DT_VER_TOLER GENMASK(27, 24) +#define VE_MODE_DT_HOR_STABLE GENMASK(23, 20) +#define VE_MODE_DT_VER_STABLE GENMASK(19, 16) +#define VE_MODE_DT_EDG_THROD GENMASK(15, 8) + #define VE_MEM_RESTRICT_START 0x310 #define VE_MEM_RESTRICT_END 0x314 @@ -1238,7 +1244,12 @@ static void aspeed_video_init_regs(struct aspeed_video *video) aspeed_video_write(video, VE_SCALING_FILTER3, 0x00200000); /* Set mode detection defaults */ - aspeed_video_write(video, VE_MODE_DETECT, 0x22666500); + aspeed_video_write(video, VE_MODE_DETECT, + FIELD_PREP(VE_MODE_DT_HOR_TOLER, 2) | + FIELD_PREP(VE_MODE_DT_VER_TOLER, 2) | + FIELD_PREP(VE_MODE_DT_HOR_STABLE, 6) | + FIELD_PREP(VE_MODE_DT_VER_STABLE, 6) | + FIELD_PREP(VE_MODE_DT_EDG_THROD, 0x65)); aspeed_video_write(video, VE_BCD_CTRL, 0); }