| Message ID | 20220118202958.1840431-3-marex@denx.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/5] clk: stm32mp1: Split ETHCK_K into separate MUX and GATE clock | expand |
> From: Marek Vasut [mailto:marex@denx.de] > Sent: Tuesday, January 18, 2022 9:30 PM > > Add another mux option for ethernet0 pins, this is used on DHCOM when > the ethernet PHY 50 MHz clock is generated by the MCO2 on PG2 pin and > then fed back via PA1 pin. > > Signed-off-by: Marek Vasut <marex@denx.de> > Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> > Cc: Christophe Roullier <christophe.roullier@foss.st.com> > Cc: Gabriel Fernandez <gabriel.fernandez@foss.st.com> > Cc: Patrice Chotard <patrice.chotard@foss.st.com> > Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> > Cc: Stephen Boyd <sboyd@kernel.org> > Cc: linux-clk@vger.kernel.org > Cc: linux-stm32@st-md-mailman.stormreply.com > To: linux-arm-kernel@lists.infradead.org > --- > arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 34 ++++++++++++++++++++++++ > 1 file changed, 34 insertions(+) > > diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi > index 3b65130affec8..2cd2ac9beaf20 100644 > --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi > +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi > @@ -338,6 +338,40 @@ pins1 { > }; > }; > > + ethernet0_rmii_pins_b: rmii-1 { > + pins1 { > + pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ > + <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ > + <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ > + <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */ > + <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ > + <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ > + bias-disable; > + drive-push-pull; > + slew-rate = <2>; > + }; > + pins2 { > + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ > + <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ > + <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ > + bias-disable; > + }; > + }; > + > + ethernet0_rmii_sleep_pins_b: rmii-sleep-1 { > + pins1 { > + pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ > + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ > + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ > + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ > + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ > + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ > + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ > + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ > + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ > + }; > + }; > + > fmc_pins_a: fmc-0 { > pins1 { > pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ > -- > 2.34.1 Tested-by: Johann Neuhauser <jneuhauser@dh-electronics.com>
Hi Marek On 1/18/22 21:29, Marek Vasut wrote: > Add another mux option for ethernet0 pins, this is used on DHCOM when > the ethernet PHY 50 MHz clock is generated by the MCO2 on PG2 pin and > then fed back via PA1 pin. > > Signed-off-by: Marek Vasut <marex@denx.de> > Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> > Cc: Christophe Roullier <christophe.roullier@foss.st.com> > Cc: Gabriel Fernandez <gabriel.fernandez@foss.st.com> > Cc: Patrice Chotard <patrice.chotard@foss.st.com> > Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> > Cc: Stephen Boyd <sboyd@kernel.org> > Cc: linux-clk@vger.kernel.org > Cc: linux-stm32@st-md-mailman.stormreply.com > To: linux-arm-kernel@lists.infradead.org > --- > arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 34 ++++++++++++++++++++++++ > 1 file changed, 34 insertions(+) > > diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi > index 3b65130affec8..2cd2ac9beaf20 100644 > --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi > +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi > @@ -338,6 +338,40 @@ pins1 { > }; > }; > > + ethernet0_rmii_pins_b: rmii-1 { > + pins1 { > + pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ > + <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ > + <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ > + <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */ > + <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ > + <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ > + bias-disable; > + drive-push-pull; > + slew-rate = <2>; > + }; > + pins2 { > + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ > + <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ > + <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ > + bias-disable; > + }; > + }; > + > + ethernet0_rmii_sleep_pins_b: rmii-sleep-1 { > + pins1 { > + pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ > + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ > + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ > + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ > + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ > + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ > + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ > + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ > + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ > + }; > + }; > + > fmc_pins_a: fmc-0 { > pins1 { > pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ Applied on stm32-next with as discussed small modifications (use xxxx_pins_c instead of xxxx_pins_b) due to conflicts with emSBC-Argon series. cheers Alex
diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 3b65130affec8..2cd2ac9beaf20 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -338,6 +338,40 @@ pins1 { }; }; + ethernet0_rmii_pins_b: rmii-1 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */ + <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ + <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + ethernet0_rmii_sleep_pins_b: rmii-sleep-1 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ + }; + }; + fmc_pins_a: fmc-0 { pins1 { pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
Add another mux option for ethernet0 pins, this is used on DHCOM when the ethernet PHY 50 MHz clock is generated by the MCO2 on PG2 pin and then fed back via PA1 pin. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Christophe Roullier <christophe.roullier@foss.st.com> Cc: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 34 ++++++++++++++++++++++++ 1 file changed, 34 insertions(+)