| Message ID | 20220119070809.15563-4-qianggui.song@amlogic.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | irqchip/meson-gpio: Add support for Meson-S4 SoC | expand |
Hi, On 19/01/2022 08:08, Qianggui Song wrote: > Due to some chips may use different registers and offset, provide > a set trigger type call back. > > Signed-off-by: Qianggui Song <qianggui.song@amlogic.com> > --- > drivers/irqchip/irq-meson-gpio.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c > index eefe15e1b3a6..b511f9532adc 100644 > --- a/drivers/irqchip/irq-meson-gpio.c > +++ b/drivers/irqchip/irq-meson-gpio.c > @@ -55,6 +55,8 @@ struct irq_ctl_ops { > void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl, > unsigned int channel, unsigned long hwirq); > void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl); > + void (*gpio_irq_sel_type)(struct meson_gpio_irq_controller *ctl, > + unsigned int idx, u32 val); > }; > > struct meson_gpio_irq_params { > @@ -278,6 +280,12 @@ static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl, > */ > type &= IRQ_TYPE_SENSE_MASK; > > + /* Some controllers may have different calculation method*/ > + if (params->ops.gpio_irq_sel_type) { > + params->ops.gpio_irq_sel_type(ctl, idx, type); > + return 0; > + } > + > /* > * New controller support EDGE_BOTH trigger. This setting takes > * precedence over the other edge/polarity settings > The comment on v1 hasn't been addresses here, it was asked to move the old controllers sel_type to a callback and introduce an S4 callback instead of doing this. Neil
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c index eefe15e1b3a6..b511f9532adc 100644 --- a/drivers/irqchip/irq-meson-gpio.c +++ b/drivers/irqchip/irq-meson-gpio.c @@ -55,6 +55,8 @@ struct irq_ctl_ops { void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl, unsigned int channel, unsigned long hwirq); void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl); + void (*gpio_irq_sel_type)(struct meson_gpio_irq_controller *ctl, + unsigned int idx, u32 val); }; struct meson_gpio_irq_params { @@ -278,6 +280,12 @@ static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl, */ type &= IRQ_TYPE_SENSE_MASK; + /* Some controllers may have different calculation method*/ + if (params->ops.gpio_irq_sel_type) { + params->ops.gpio_irq_sel_type(ctl, idx, type); + return 0; + } + /* * New controller support EDGE_BOTH trigger. This setting takes * precedence over the other edge/polarity settings
Due to some chips may use different registers and offset, provide a set trigger type call back. Signed-off-by: Qianggui Song <qianggui.song@amlogic.com> --- drivers/irqchip/irq-meson-gpio.c | 8 ++++++++ 1 file changed, 8 insertions(+)