From patchwork Thu Jan 20 11:30:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Clark X-Patchwork-Id: 12718555 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1ACAFC433FE for ; Thu, 20 Jan 2022 11:32:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=zD0hBwvn6D6cQ+Qj8ZzIVbn9rNiljyE06WzyvOl3Mqk=; b=XoMNEH+l721GU2 cPumCGSNXYPl6R3JtMDefZXhGUb0c7A2euLjl0E9Zr9/GumoFQtDFFi2yqAagndV5LirqSTRWc5mi 4UtwWzMxopWUn8ko99tSTod1it0Gt0WUKqXsSz5S8CUL0LSpzdi/OjtxzDe+TGGm0NV+uVKGJUrI1 97JLS/K/RDAPf1LPhibdoXSFjtvQjgx5ZzOqokued0QLzEKjp9/56dyKoHWl8d/cvp3diEZ3Bm9a/ ns07qahZfzY/Po+p6CrzK2FzgZo5NMoXHFV0OtyzLvfdCysDHIsvpaWU+kttVbw2ilanG3SlglfjN plcavqGk/O2fCMAGLjPg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nAVev-00B4l4-S5; Thu, 20 Jan 2022 11:31:17 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nAVeh-00B4hs-Nw for linux-arm-kernel@lists.infradead.org; Thu, 20 Jan 2022 11:31:05 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7CE47101E; Thu, 20 Jan 2022 03:31:02 -0800 (PST) Received: from e121896.arm.com (unknown [10.57.37.233]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9CCD63F774; Thu, 20 Jan 2022 03:31:00 -0800 (PST) From: James Clark To: mathieu.poirier@linaro.org, coresight@lists.linaro.org, mike.leach@linaro.org Cc: suzuki.poulose@arm.com, leo.yan@linaro.com, James Clark , Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/1] coresight: Fix TRCCONFIGR.QE sysfs interface Date: Thu, 20 Jan 2022 11:30:47 +0000 Message-Id: <20220120113047.2839622-2-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220120113047.2839622-1-james.clark@arm.com> References: <20220120113047.2839622-1-james.clark@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220120_033103_846479_D60F1A82 X-CRM114-Status: GOOD ( 14.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org It's impossible to program a valid value for TRCCONFIGR.QE when TRCIDR0.QSUPP==0b10. In that case the following is true: Q element support is implemented, and only supports Q elements without instruction counts. TRCCONFIGR.QE can only take the values 0b00 or 0b11. Currently the low bit of QSUPP is checked to see if the low bit of QE can be written to, but as you can see when QSUPP==0b10 the low bit is cleared making it impossible to ever write the only valid value of 0b11 to QE. 0b10 would be written instead, which is a reserved QE value even for all values of QSUPP. The fix is to allow writing the low bit of QE for any non zero value of QSUPP. This change also ensures that the low bit is always set, even when the user attempts to only set the high bit. Signed-off-by: James Clark Reviewed-by: Mike Leach --- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index a0640fa5c55b..57e94424a8d6 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -367,8 +367,12 @@ static ssize_t mode_store(struct device *dev, mode = ETM_MODE_QELEM(config->mode); /* start by clearing QE bits */ config->cfg &= ~(BIT(13) | BIT(14)); - /* if supported, Q elements with instruction counts are enabled */ - if ((mode & BIT(0)) && (drvdata->q_support & BIT(0))) + /* + * if supported, Q elements with instruction counts are enabled. + * Always set the low bit for any requested mode. Valid combos are + * 0b00, 0b01 and 0b11. + */ + if (mode && drvdata->q_support) config->cfg |= BIT(13); /* * if supported, Q elements with and without instruction