From patchwork Sat Jan 29 19:36:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 12729630 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7C62C433EF for ; Sat, 29 Jan 2022 19:40:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Cc:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=g8tK9ojVJr5HI7IUF8+PsQRx8VTwVBtjb9FTGWJg4VA=; b=bUc3U8hE9WLjxG S6NkpYLa81fU3qjlR3M8PGa41mr+CB6l99tGExW6QI+alVJrkd/wDzS9PvaedWDvw3ssEAuyjb003 KZUVSbki8gpbGfLZKOZN3Tsv9uhl7ShtBK/LMy8Jl4yDp6psZnKjlAn1jQpik+rT6yLxmRYucfvdV YHhWH8o5Sg2UGifqU1UxV8NWnbPmBb0cXETDWDylfg5aM0fXyxefjS+RwJQgvtpZ6wr41Ybddqk6v hc870EOy9elL/2uBJbBljA16lJcltFRW8qWzEXK7x3yS5VRbwLOFcEi0L/8w3rrNJzM6TeGTISI1w U8Xu/L+h1fonatNTInNA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nDtYm-005Kbz-0u; Sat, 29 Jan 2022 19:38:56 +0000 Received: from smtp-relay-internal-0.canonical.com ([185.125.188.122]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nDtXC-005Jyu-Uc for linux-arm-kernel@lists.infradead.org; Sat, 29 Jan 2022 19:37:21 +0000 Received: from mail-ed1-f72.google.com (mail-ed1-f72.google.com [209.85.208.72]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-0.canonical.com (Postfix) with ESMTPS id 5620F4076E for ; Sat, 29 Jan 2022 19:37:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1643485031; bh=v3MaE4YE81127QeF4TU2Qxtg0ok0vmr5F1s7ZnnGBgk=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Mdcv8aHzmOU+HGPqXsl/p9v+P3RSOg8+ecPVqa1gYYsbC7pzlyaHBTjRI6QipRin/ 8L07fG2HyswAMXjSt99VtNqi/7gMpR21TTrVpjrRlTX3dFm0Bkly6pR59fYDQyo2Z9 wWpLAwQp5dbQhkpEzlIw4u/ipyi0QygNMudb36HqhK56eNIGBWY6x4fjgRGE9UmS0x 4oA75nxIALYRoCeT60o3Hfg+0QstJsefdJWN0uwxa/bnM9Eefe1I1xEzpqarblR4eC +oRhl+Y7pPLrXZEIT4jCW/UIrcsafkDJEJKs7s5eKQ5pwdU/BXpUr3qztEGbtEKdQ3 Uwtt+qiXSW99w== Received: by mail-ed1-f72.google.com with SMTP id bc24-20020a056402205800b00407cf07b2e0so4798258edb.8 for ; Sat, 29 Jan 2022 11:37:11 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v3MaE4YE81127QeF4TU2Qxtg0ok0vmr5F1s7ZnnGBgk=; b=L+j/Bsh6Hw3Maw23wGClexADtLEVqMbFH0sT0AkP/Z9da7ivAZnEjNb9UFeRkgjeSA vjQW4GCSIL87MAfPVK4fpKlvf3hZc/wOoqzBd0Fw+KIkkNKcp7kzhfpklaYS0B99kuec zWCrtGsNL77qssI4heyPg8x9jEnDkLhBxQFeKxhE6+zlArcuzgPvwRBl17hR5J3SF5IA /aeGF7u//AEm1eNr+PjAQ4eiAR+QePnYUOKbbrkMpmUzZ+MZ4JyVRZ2DMFy7K28ziGh9 vh3LQe9gvTAMdtlMOtd2WL1DqR//I0w4J91VitC36z+pzWgaP2amIn5b3pCh3n2hgPeX SUgg== X-Gm-Message-State: AOAM531atlWpwAl2qKp82PUHgFQASMV1Mq8m9Pr36EdWmZTPdia/G5UF 45zwq/7KtC3fqqQbBEuQnn4xs5mnkYIyhEDvWmZzU+0H3EdMN95idUjpb2kuH54h0eUAsrisino xhlzd/4Rdo8Lf2yhlOSmWupMqJd4ndVxOAJYgILEoS3Lgkczrqlel X-Received: by 2002:aa7:d709:: with SMTP id t9mr13957567edq.216.1643485019380; Sat, 29 Jan 2022 11:36:59 -0800 (PST) X-Google-Smtp-Source: ABdhPJzxLkvcLW6BLxgIqLjTWWRLCLYPN6D4UhxKK1OqrkVsROsoJ44oBC30s8nc7egAVFljLNwTyw== X-Received: by 2002:aa7:d709:: with SMTP id t9mr13957561edq.216.1643485019174; Sat, 29 Jan 2022 11:36:59 -0800 (PST) Received: from localhost.localdomain (xdsl-188-155-168-84.adslplus.ch. [188.155.168.84]) by smtp.gmail.com with ESMTPSA id bf21sm14968026edb.2.2022.01.29.11.36.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Jan 2022 11:36:58 -0800 (PST) From: Krzysztof Kozlowski To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , Sylwester Nawrocki , Guenter Roeck , Marek Szyprowski , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 8/8] dt-bindings: phy: samsung, usb3-drd-phy: convert to dtschema Date: Sat, 29 Jan 2022 20:36:46 +0100 Message-Id: <20220129193646.372481-8-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220129193646.372481-1-krzysztof.kozlowski@canonical.com> References: <20220129193646.372481-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220129_113719_166479_4F5F7A7F X-CRM114-Status: GOOD ( 22.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert the Samsung Exynos USB 3.0 DRD PHY bindings to DT schema format. Except the conversion, add also vbus-supply and vbus-boost-supply properties which were already used by the driver and DTS. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- .../bindings/phy/samsung,usb3-drd-phy.yaml | 126 ++++++++++++++++++ .../devicetree/bindings/phy/samsung-phy.txt | 53 -------- 2 files changed, 126 insertions(+), 53 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml delete mode 100644 Documentation/devicetree/bindings/phy/samsung-phy.txt diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml new file mode 100644 index 000000000000..f83f0f8135b9 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC USB 3.0 DRD PHY USB 2.0 PHY + +maintainers: + - Krzysztof Kozlowski + - Marek Szyprowski + - Sylwester Nawrocki + +description: | + For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy + compatible PHYs, the second cell in the PHY specifier identifies the + PHY id, which is interpreted as follows:: + 0 - UTMI+ type phy, + 1 - PIPE3 type phy. + + For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers, + 'usbdrd_phy' nodes should have numbered alias in the aliases node, in the + form of usbdrdphyN, N = 0, 1... (depending on number of controllers). + +properties: + compatible: + enum: + - samsung,exynos5250-usbdrd-phy + - samsung,exynos5420-usbdrd-phy + - samsung,exynos5433-usbdrd-phy + - samsung,exynos7-usbdrd-phy + + clocks: + minItems: 2 + maxItems: 5 + + clock-names: + minItems: 2 + maxItems: 5 + description: | + At least two clocks:: + - Main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), used + for register access. + - PHY reference clock (usually crystal clock), used for PHY operations, + associated by phy name. It is used to determine bit values for clock + settings register. For Exynos5420 this is given as 'sclk_usbphy30' + in the CMU. + + "#phy-cells": + const: 1 + + port: + $ref: /schemas/graph.yaml#/properties/port + description: + Any connector to the data bus of this controller should be modelled using + the OF graph bindings specified. + + reg: + maxItems: 1 + + samsung,pmu-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to PMU system controller interface. + + vbus-supply: + description: + VBUS power source. + + vbus-boost-supply: + description: + VBUS Boost 5V power source. + +required: + - compatible + - clocks + - clock-names + - "#phy-cells" + - reg + - samsung,pmu-syscon + +allOf: + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos5433-usbdrd-phy + - samsung,exynos7-usbdrd-phy + then: + properties: + clocks: + minItems: 5 + maxItems: 5 + clock-names: + items: + - const: phy + - const: ref + - const: phy_utmi + - const: phy_pipe + - const: itp + else: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: phy + - const: ref + +additionalProperties: false + +examples: + - | + #include + + phy@12100000 { + compatible = "samsung,exynos5420-usbdrd-phy"; + reg = <0x12100000 0x100>; + #phy-cells = <1>; + clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; + vbus-supply = <&usb300_vbus_reg>; + }; diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt deleted file mode 100644 index b0abeb4ac0a2..000000000000 --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt +++ /dev/null @@ -1,53 +0,0 @@ -Samsung Exynos5 SoC series USB DRD PHY controller --------------------------------------------------- - -Required properties: -- compatible : Should be set to one of the following supported values: - - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC, - - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC. - - "samsung,exynos5433-usbdrd-phy" - for exynos5433 SoC. - - "samsung,exynos7-usbdrd-phy" - for exynos7 SoC. -- reg : Register offset and length of USB DRD PHY register set; -- clocks: Clock IDs array as required by the controller -- clock-names: names of clocks correseponding to IDs in the clock property; - Required clocks: - - phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), - used for register access. - - ref: PHY's reference clock (usually crystal clock), used for - PHY operations, associated by phy name. It is used to - determine bit values for clock settings register. - For Exynos5420 this is given as 'sclk_usbphy30' in CMU. - - optional clocks: Exynos5433 & Exynos7 SoC has now following additional - gate clocks available: - - phy_pipe: for PIPE3 phy - - phy_utmi: for UTMI+ phy - - itp: for ITP generation -- samsung,pmu-syscon: phandle for PMU system controller interface, used to - control pmu registers for power isolation. -- #phy-cells : from the generic PHY bindings, must be 1; - -For "samsung,exynos5250-usbdrd-phy" and "samsung,exynos5420-usbdrd-phy" -compatible PHYs, the second cell in the PHY specifier identifies the -PHY id, which is interpreted as follows: - 0 - UTMI+ type phy, - 1 - PIPE3 type phy, - -Example: - usbdrd_phy: usbphy@12100000 { - compatible = "samsung,exynos5250-usbdrd-phy"; - reg = <0x12100000 0x100>; - clocks = <&clock 286>, <&clock 1>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <1>; - }; - -- aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers, - 'usbdrd_phy' nodes should have numbered alias in the aliases node, - in the form of usbdrdphyN, N = 0, 1... (depending on number of - controllers). -Example: - aliases { - usbdrdphy0 = &usb3_phy0; - usbdrdphy1 = &usb3_phy1; - };