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[146.115.144.188]) by smtp.gmail.com with ESMTPSA id h12sm7556651qkp.129.2022.01.30.14.03.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Jan 2022 14:03:30 -0800 (PST) From: Jesse Taube X-Google-Original-From: Jesse Taube To: devicetree@vger.kernel.org Cc: robh+dt@kernel.org, Mr.Bossman075@gmail.com, andre.przywara@arm.com, linux-sunxi@lists.linux.dev, mripard@kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 3/4] ARM: dtsi: suniv: Add mmc to f1c100s dtsi. Date: Sun, 30 Jan 2022 17:03:24 -0500 Message-Id: <20220130220325.1983918-3-Mr.Bossman075@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220130220325.1983918-1-Mr.Bossman075@gmail.com> References: <20220130220325.1983918-1-Mr.Bossman075@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220130_140331_753218_9C583F01 X-CRM114-Status: GOOD ( 10.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add mmc0 and 1 for f1c100s dtsi. Signed-off-by: Jesse Taube --- V1 -> V2: * Split patch --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 41 ++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 953228cc8d52..60fa56c278a8 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -96,6 +96,11 @@ uart0_pe_pins: uart0-pe-pins { pins = "PE0", "PE1"; function = "uart0"; }; + + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; + function = "mmc0"; + }; }; timer@1c20c00 { @@ -111,6 +116,42 @@ wdt: watchdog@1c20ca0 { reg = <0x01c20ca0 0x20>; }; + mmc0: mmc@1c0f000 { + compatible = "allwinner,suniv-f1c100s-mmc", + "allwinner,sun7i-a20-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; + clock-names = "ahb", "mmc", "output", "sample"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = <23>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@1c10000 { + compatible = "allwinner,suniv-f1c100s-mmc", + "allwinner,sun7i-a20-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; + clock-names = "ahb", "mmc", "output", "sample"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = <24>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + uart0: serial@1c25000 { compatible = "snps,dw-apb-uart"; reg = <0x01c25000 0x400>;