From patchwork Mon Feb 7 03:24:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12736804 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 746AFC433F5 for ; Mon, 7 Feb 2022 03:25:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=SPKzkWtfvl/NTwx8yA0YCM1WvQ8uvJaabJiXb3WSizU=; b=siSdEL972vw9ZU ysOAwNJ7R/Q+FtnF8bAKQGJSboEBRyGuRHIir8TM/RyLFiQPMr9gtgE7QzLmAXBqpB0DAcZiDj5ZU ZE98c/QB4/wUUi/TJcU+QNeuTYRD1AyanAx5xjwX25iAKxlMlrOCuHXfJmaWZwb64YjtYPj/vJe6F /fB57jLpu69f6nGO7pXPNWUdw71OW1RM05DJmAN93hn/8FKPx97rGsXOxTTilRqKQjRzJ+pPWkNGT vjdS5C4GIJ1ekde90CyWG2BiwU45jSZhzw7EVYlkTBrwa3i5KTw1QjkkXep1p0CSko5LPGyu+8+8F C5qCfwQAdaZ7WWFA7vww==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nGudw-008wGN-UR; Mon, 07 Feb 2022 03:24:45 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nGudX-008wC7-QM for linux-arm-kernel@lists.infradead.org; Mon, 07 Feb 2022 03:24:21 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1644204259; x=1675740259; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6WoxkUkguy8rx/vdMwuFD/M1zus/du+BiEWUk2id+LM=; b=vPxXfUdpv12NYNmWczl6WTDJYJaxHlEQKZtAhwEv+mcU2a//Szbd3sHU kps+/OrRUPQqSHAp+CXJ+Z+D2kN0swFgamooiF7b2Enu/SEyvKT1Ng0p/ J7xvDihtcs1A7oGhseOWZklZX/w1V/dt3OQwMdFbqHoICtjH7hS0YxTO+ UpjHFzZls6Mg7RcZJYhfAiFbjA4Lw9/I9ztRYyDQe/UCRAlulrnfhc1p3 Fl3WJuqDMifBgOG2/98K8POKvVwH7HvPlDr1L/a/1ALpsx7B+jWs/+W85 w0ZLdDELYSqAb5Cf8rYk0sCJz3yEEV1d5GaMp+r8pf8UGLxwld4JDI5oa A==; IronPort-SDR: kZCMQKK8MQiDSTQxgzF25qDB32EjuHAbxIFHT/exe1J7tlWvHsomMzaGbkX1rrVlKeJPSZij32 AeTpkdNPWYAJ1bn1cok7H5ELU5HquaxbqrCKfhTerocT1DBrwnlQ0m5+aIhoe7ZZuBdNgVlSp6 yQ6n8kNRJOTg7WbPfO56j2esbG0fYy88f9CF/udrsfybp/95/ZMbEzFkYJWOTKMsoYrRPeX5RY OoMzRfMOwBa18HHV0u5OL+ajfC4GfZVPvDiFmJ+x0kZdOLUtKHZecI1w9cjO/tErFBkq2rLOCs 54ZefkRcDURwnacr3A61SX/m X-IronPort-AV: E=Sophos;i="5.88,348,1635231600"; d="scan'208";a="147803329" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Feb 2022 20:24:19 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Sun, 6 Feb 2022 20:24:18 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Sun, 6 Feb 2022 20:24:16 -0700 From: Tudor Ambarus To: , Subject: [PATCH 3/3] dt-bindings: crypto: Convert Atmel SHA to yaml Date: Mon, 7 Feb 2022 05:24:05 +0200 Message-ID: <20220207032405.70733-4-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220207032405.70733-1-tudor.ambarus@microchip.com> References: <20220207032405.70733-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220206_192419_976129_8ABB52BB X-CRM114-Status: GOOD ( 13.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, alexandre.belloni@bootlin.com, Tudor Ambarus , linux-kernel@vger.kernel.org, davem@davemloft.net, linux-crypto@vger.kernel.org, claudiu.beznea@microchip.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert Atmel SHA documentation to yaml format. With the conversion the clock and clock-names properties are made mandatory. The driver returns -EINVAL if "sha_clk" is not found, reflect that in the bindings and make the clock and clock-names properties mandatory. Update the example to better describe how one should define the dt node. Signed-off-by: Tudor Ambarus --- .../devicetree/bindings/crypto/atmel,sha.yaml | 59 +++++++++++++++++++ .../bindings/crypto/atmel-crypto.txt | 25 -------- 2 files changed, 59 insertions(+), 25 deletions(-) create mode 100644 Documentation/devicetree/bindings/crypto/atmel,sha.yaml delete mode 100644 Documentation/devicetree/bindings/crypto/atmel-crypto.txt diff --git a/Documentation/devicetree/bindings/crypto/atmel,sha.yaml b/Documentation/devicetree/bindings/crypto/atmel,sha.yaml new file mode 100644 index 000000000000..ccba6d36ee68 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/atmel,sha.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/atmel,sha.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel Secure Hash Algorithm (SHA) HW cryptographic accelerator + +maintainers: + - Tudor Ambarus + +properties: + compatible: + const: atmel,at91sam9g46-sha + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: sha_clk + + dmas: + maxItems: 1 + description: TX DMA Channel + + dma-names: + const: tx + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + sha: sha@e1814000 { + compatible = "atmel,at91sam9g46-sha"; + reg = <0xe1814000 0x100>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 83>; + clock-names = "sha_clk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>; + dma-names = "tx"; + status = "okay"; + }; diff --git a/Documentation/devicetree/bindings/crypto/atmel-crypto.txt b/Documentation/devicetree/bindings/crypto/atmel-crypto.txt deleted file mode 100644 index 5c6541cfcc4a..000000000000 --- a/Documentation/devicetree/bindings/crypto/atmel-crypto.txt +++ /dev/null @@ -1,25 +0,0 @@ -* Atmel HW cryptographic accelerators - -These are the HW cryptographic accelerators found on some Atmel products. - -* Secure Hash Algorithm (SHA) - -Required properties: -- compatible : Should be "atmel,at91sam9g46-sha". -- reg: Should contain SHA registers location and length. -- interrupts: Should contain the IRQ line for the SHA. - -Optional properties: -- dmas: One DMA specifiers as described in - atmel-dma.txt and dma.txt files. -- dma-names: Contains one identifier string for each DMA specifier - in the dmas property. Only one "tx" string needed. - -Example: -sha@f8034000 { - compatible = "atmel,at91sam9g46-sha"; - reg = <0xf8034000 0x100>; - interrupts = <42 4 0>; - dmas = <&dma1 2 17>; - dma-names = "tx"; -};