From patchwork Wed Feb 9 10:57:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 12740093 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 17043C433EF for ; Wed, 9 Feb 2022 10:59:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=IFC7IZWxmOBEjlJdaD92jGCtnqqisnz8hQUTeyWywqc=; b=AwjhGFJY9GvGWn tfQDia4eabTu7/s+2QwN1G7zNxJbZo66B7WKY1e90Q3xEN+D+Yb3K3tZzdmBryXBD8nb34lZ+eTkw +1jxdgZxo2+veIx/SSKDnBy2VzO31Jk9NzBcZY7DBUBEATBlTOg/kAH5kf+IQBwkhhcEZ7mJQQbVp xtro2WfwYQ2rkK90na3mqFc1OKncl5b036Jl5d/lDkrIlAa764mA/hpFgzA+JwM2uif0m3D3om5mz FyTeaRM+i8OxbbprJRDKc7ovoL7Z2Awe+FBPaFNd0CLNO8WRTZC7mRNaPor4BJvS3RJkFmT6soEw3 PblCrgr6ADRPbOtttTkg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nHkgH-00HLl9-Az; Wed, 09 Feb 2022 10:58:37 +0000 Received: from alexa-out.qualcomm.com ([129.46.98.28]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nHkfW-00HLUu-1u for linux-arm-kernel@lists.infradead.org; Wed, 09 Feb 2022 10:57:51 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1644404270; x=1675940270; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=ymNRMu+gBg6OvkS+IUc6XUhPjfMnKryjA5CxUcBOeo4=; b=Zu4T1MolecHXeH66vnXyXAhPN0usKP7zGGfdbOhOnAuoyYk+VdYGMWyX xsT8FJQ/YJbytFrP/JPQcKDC9EskpbhinQQ9pAE/XRxa73rzCvJijT+qD V/pCx3ifOCH2JpzUXyzNx/YOrd9KFgCJhaW2FAFa+6B7e+wxORBo2ntkx Q=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 09 Feb 2022 02:57:50 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 02:57:49 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Wed, 9 Feb 2022 02:57:48 -0800 Received: from jinlmao-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Wed, 9 Feb 2022 02:57:45 -0800 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin CC: Mao Jinlong , Mike Leach , Leo Yan , Greg Kroah-Hartman , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Hao Zhang , Subject: [PATCH v3 05/10] coresight-tpdm: Add DSB dataset support Date: Wed, 9 Feb 2022 18:57:01 +0800 Message-ID: <20220209105706.18852-6-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220209105706.18852-1-quic_jinlmao@quicinc.com> References: <20220209105706.18852-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220209_025750_181681_D723D7C7 X-CRM114-Status: GOOD ( 19.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org TPDM serves as data collection component for various dataset types. DSB(Discrete Single Bit) is one of the dataset types. DSB subunit can be enabled for data collection by writing 1 to the first bit of DSB_CR register. This change is to add enable/disable function for DSB dataset by writing DSB_CR register. Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong --- drivers/hwtracing/coresight/coresight-tpdm.c | 57 ++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 21 ++++++++ 2 files changed, 78 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 51b8b17e6a80..c6480b7389b0 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -20,7 +20,28 @@ DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm"); +static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) +{ + u32 val; + + /* Set the enable bit of DSB control register to 1 */ + val = readl_relaxed(drvdata->base + TPDM_DSB_CR); + val = val | BIT(0); + writel_relaxed(val, drvdata->base + TPDM_DSB_CR); +} + /** TPDM enable operations **/ +static void _tpdm_enable(struct tpdm_drvdata *drvdata) +{ + CS_UNLOCK(drvdata->base); + + /* Check if DSB datasets is present for TPDM. */ + if (test_bit(TPDM_DS_DSB, drvdata->datasets)) + tpdm_enable_dsb(drvdata); + + CS_LOCK(drvdata->base); +} + static int tpdm_enable(struct coresight_device *csdev, struct perf_event *event, u32 mode) { @@ -32,6 +53,7 @@ static int tpdm_enable(struct coresight_device *csdev, return -EBUSY; } + _tpdm_enable(drvdata); drvdata->enable = true; mutex_unlock(&drvdata->lock); @@ -39,7 +61,29 @@ static int tpdm_enable(struct coresight_device *csdev, return 0; } +static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata) +{ + u32 val; + + /* Set the enable bit of DSB control register to 0 */ + val = readl_relaxed(drvdata->base + TPDM_DSB_CR); + val = val & ~BIT(0); + writel_relaxed(val, drvdata->base + TPDM_DSB_CR); +} + /** TPDM disable operations **/ +static void _tpdm_disable(struct tpdm_drvdata *drvdata) +{ + CS_UNLOCK(drvdata->base); + + /* Check if DSB datasets is present for TPDM. */ + if (test_bit(TPDM_DS_DSB, drvdata->datasets)) + tpdm_disable_dsb(drvdata); + + CS_LOCK(drvdata->base); + +} + static void tpdm_disable(struct coresight_device *csdev, struct perf_event *event) { @@ -51,6 +95,7 @@ static void tpdm_disable(struct coresight_device *csdev, return; } + _tpdm_disable(drvdata); drvdata->enable = false; mutex_unlock(&drvdata->lock); @@ -76,7 +121,19 @@ static const struct coresight_ops tpdm_cs_ops = { static void tpdm_init_default_data(struct tpdm_drvdata *drvdata) { + int i; + u32 pidr; + drvdata->traceid = coresight_get_system_trace_id(); + + CS_UNLOCK(drvdata->base); + /* Get the datasets present on the TPDM. */ + pidr = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR0); + for (i = 0; i < TPDM_DATASETS; i++) { + if (pidr & BIT(i)) + __set_bit(i, drvdata->datasets); + } + CS_LOCK(drvdata->base); } static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 2effbabf349b..cb3ddc6c89ae 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -6,6 +6,25 @@ #ifndef _CORESIGHT_CORESIGHT_TPDM_H #define _CORESIGHT_CORESIGHT_TPDM_H +/* The max number of the datasets that TPDM supports */ +#define TPDM_DATASETS 7 + +/* DSB Subunit Registers */ +#define TPDM_DSB_CR (0x780) + +/** + * This enum is for PERIPHIDR0 register of TPDM. + * The fields [6:0] of PERIPHIDR0 are used to determine what + * interfaces and subunits are present on a given TPDM. + * + * PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0 + * PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0 + */ +enum tpdm_dataset { + TPDM_DS_IMPLDEF, + TPDM_DS_DSB, +}; + /** * struct tpdm_drvdata - specifics associated to an TPDM component * @base: memory mapped base address for this component. @@ -13,6 +32,7 @@ * @csdev: component vitals needed by the framework. * @lock: lock for the enable value. * @enable: enable status of the component. + * @datasets: The datasets types present of the TPDM. * @traceid: value of the current ID for this component. */ @@ -22,6 +42,7 @@ struct tpdm_drvdata { struct coresight_device *csdev; struct mutex lock; bool enable; + DECLARE_BITMAP(datasets, TPDM_DATASETS); int traceid; };