From patchwork Wed Feb 9 18:47:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 12740789 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 32DEBC433FE for ; Wed, 9 Feb 2022 18:59:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=w6PNi0Cw5Ij8lqLJLVCCu0d3wH8nVzTP4+ioDA1qEak=; b=FeKd33pXTU7qtS hpzU0qbK4YVYfwpRhWcshxN2JctZzkZpUYlCky/yVNJ/T8OtQke583zBEtrR6NQgbb8XJMdKNin8V DfLFW9726REmyH0wA8rOvMRZcel6HmUKijecjPrsyHdEXheuhiWzS2211opNNZH5JT07+MRieo198 hAQEvaY3HHy7ZQPwz7ZX2pIV7hv/QgI0CfvR+NvDZnTZ0c3lWJ5rtUKN//t8h4mMCuOIVK+a9Rt8Q jBVcUlgBrZfy055W34vEOlOPea1tRegaI9Zbzz9KCqh3VwNYcV0lr0aXusRDci59Ha40bg4NfpSBX SYLhFaLhEC8HnCoMTlww==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nHs9T-001G3W-Rt; Wed, 09 Feb 2022 18:57:16 +0000 Received: from mga11.intel.com ([192.55.52.93]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nHs0N-001Cir-DW for linux-arm-kernel@lists.infradead.org; Wed, 09 Feb 2022 18:47:53 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644432471; x=1675968471; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=J/7XQfjKt9d3myGcrh1l1pOHrCE5f9w0ySm6uM+4N84=; b=dYbSF5dVgvHkHeanx9GttxfgP1QCBTu+bUricM6Gd61Q7h/din/gwK/z vcthcKmHT9ifblu18pNtoB6vu88uaOA4VpTcGx+NU0jsp5xf6cuUAb+TR Uaauv5BAa9vj8owg8UIwvY67CdUcF83Uv3vTEM9akTs2uwJUDwQqz6CZa ugNHhxN40hWvRTz7GKl7VcArnCHO+bc4dx8Tf6AOrYHgSi1FAw8TT8HU7 TKG7nkWqW0e0Lsr3SLO5G5deeTNR/MKb5u/Xzqu2oA0E6n0J8ZVZA6RMB wvRjYLmgYsLecCYYqZ87ViGCeMCamgTKtR7ROAiuS5dzhdt++otdec2gX Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10252"; a="246886531" X-IronPort-AV: E=Sophos;i="5.88,356,1635231600"; d="scan'208";a="246886531" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 10:47:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,356,1635231600"; d="scan'208";a="541245172" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga008.jf.intel.com with ESMTP; 09 Feb 2022 10:47:49 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 2C02D107; Wed, 9 Feb 2022 20:48:03 +0200 (EET) From: Andy Shevchenko To: Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Andy Shevchenko Subject: [PATCH v1 1/1] perf/smmuv3: Don't cast parameter in bit operations Date: Wed, 9 Feb 2022 20:47:58 +0200 Message-Id: <20220209184758.56578-1-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220209_104751_843079_0F68A536 X-CRM114-Status: GOOD ( 14.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org While in this particular case it would not be a (critical) issue, the pattern itself is bad and error prone in case somebody blindly copies to their code. Don't cast parameter to unsigned long pointer in the bit operations. Instead copy to a local variable on stack of a proper type and use. Note, new compilers might warn on this line for potential outbound access. Fixes: 7d839b4b9e00 ("perf/smmuv3: Add arm64 smmuv3 pmu driver") Signed-off-by: Andy Shevchenko Reviewed-by: Robin Murphy --- drivers/perf/arm_smmuv3_pmu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c index c49108a72865..00d4c45a8017 100644 --- a/drivers/perf/arm_smmuv3_pmu.c +++ b/drivers/perf/arm_smmuv3_pmu.c @@ -654,6 +654,7 @@ static int smmu_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node) static irqreturn_t smmu_pmu_handle_irq(int irq_num, void *data) { struct smmu_pmu *smmu_pmu = data; + DECLARE_BITMAP(ovs, BITS_PER_TYPE(u64)); u64 ovsr; unsigned int idx; @@ -663,7 +664,8 @@ static irqreturn_t smmu_pmu_handle_irq(int irq_num, void *data) writeq(ovsr, smmu_pmu->reloc_base + SMMU_PMCG_OVSCLR0); - for_each_set_bit(idx, (unsigned long *)&ovsr, smmu_pmu->num_counters) { + bitmap_from_u64(ovs, ovsr); + for_each_set_bit(idx, ovs, smmu_pmu->num_counters) { struct perf_event *event = smmu_pmu->events[idx]; struct hw_perf_event *hwc;