From patchwork Thu Feb 10 12:03:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kavyasree Kotagiri X-Patchwork-Id: 12741831 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4AF42C433EF for ; Thu, 10 Feb 2022 12:05:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=le1MXLXVqR96lNE45WgKloWh39k02W+VPbyR+UXBsXs=; b=Y+ggKGRKMU3kKS D/YLAP5CcBRcncNR1Y6ZiRIr3e4p1onR0abYQuQdR2GaOEl6lUBKieNCw0wtMxOlsQrWiQFix37rl x+A1g8sKROUbpaJx6z65iYYUZR7YTnLk/sEOnDinQHIfSzyjbDT54+9PfWLN2QORgzYYJjSHltOfG iiZ8VxoGVtvl9IhiDYS+nbhk1Ikm6EdiL+v+OeWFBHdcHnb0mpeeyK/iQlOc27coDAzS/WOoxnc+I aIck73aU8k8mL/urGythaITftHPqgG8RCF8Lrg8eWM6IM5YOjWqzFORcfV3PWN0D2Ik7rQtPfovlp 7f2nWUEMfB3uLBw14AKQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nI8B5-003huO-IM; Thu, 10 Feb 2022 12:03:59 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nI8B1-003hst-FG for linux-arm-kernel@lists.infradead.org; Thu, 10 Feb 2022 12:03:57 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1644494635; x=1676030635; h=from:to:cc:subject:date:message-id:mime-version; bh=/QlpKJ0CM3BFbESDBVfYSFlxY6nL1RIf7FZPBAXC1J4=; b=n6LdQkDDJZWwWHxl+BtO5474LQGNlJdlccRrhiaDY3sN/dfGsMOzI9hd yxQBHfTEb7zcaDmAg2Cwp+esFIvlP8Hb972tlM+WPsWsULSsLg1vUSsvy EPfq4rBT0ao8fWf8Pa5RVt9nixSaqgWHm30CnCzkhBM8wBnzEZr0tELx7 P09kspXuA7XcI3XNe7s3+EEf7kBusKTQ09Ko+ydTHjCxPAviAMJkrAu+Q /P960fcc63iICbQe1xP6dcRjdGB2bh1nbDbm6n/uC/Q5EJNH1jAdttP6e MFrfZ1ApiSRJ+MBvTmJeIZIVehYgDc6cWw6g7dN+tSZwDES2m6Zl4wPRm w==; IronPort-SDR: LJriOWYn+YqpKnw+ulSGha3eA0bTulDnE98gm11dqVy1QE5O5e7lGRY9Kz7c015Ruju9+eDcZ1 tcK0Lq/u5WBgJ1AK5SjQXtBrLfKSuXft0KFaRaJiG9GFXkzA3sf6KZv+J9/eFgRpnmNAFYRdKU Px2TyJeucbelYE2ebWHGmP661F+FAGTxA9okAN681AdBZJ06JSbjd+5njQJ79SbvAjdDUaUtho 75keb4qIiPyRlsoHzu0TKpoVCWR35FYCyLU9fddyN2F/wmWoPTMZFIdWmqem63lm17AUtEHDFI SOENjePYjNWbiL7MyvMSEpQu X-IronPort-AV: E=Sophos;i="5.88,358,1635231600"; d="scan'208";a="85296846" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 10 Feb 2022 05:03:52 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 10 Feb 2022 05:03:51 -0700 Received: from kavya-HP-Compaq-6000-Pro-SFF-PC.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 10 Feb 2022 05:03:47 -0700 From: Kavyasree Kotagiri To: , , , , , CC: , , , , , Subject: [PATCH v5] ARM: dts: add DT for lan966 SoC and 2-port board pcb8291 Date: Thu, 10 Feb 2022 17:33:19 +0530 Message-ID: <20220210120319.32190-1-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220210_040355_604880_9018A465 X-CRM114-Status: GOOD ( 15.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds basic DT for Microchip lan966x SoC and associated board pcb8291(2-port EVB). Adds peripherals required to allow booting: Interrupt Controller, Clock, Generic ARMv7 Timers, Synopsys Timer, Flexcoms, GPIOs. Also adds other peripherals like crypto(AES/SHA), DMA, Watchdog Timer, TRNG and MCAN0. Signed-off-by: Kavyasree Kotagiri --- v4 -> v5: - Modified AES, SHA, TRNG node names as per generic names recommended. v3 -> v4: - Removed character 'x' from compatible string. - Removed memory node as handled by bootloader. - Renamed flexcom3 usart0 to usart3 - Added /chosen and /aliases nodes in dts file. v2 -> v3: - Enabling trng in dtsi itself. - Removed "status=okay" dma0. - Add gpio pin settings for can0(missed adding this in previous version) v1 -> v2: - Moved flx3 usart0 node to dtsi file. - Removed status="okay" for dma0 to maintain consistency across nodes (which means enabling dma0 by default) arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/lan966x.dtsi | 237 ++++++++++++++++++++++++++ arch/arm/boot/dts/lan966x_pcb8291.dts | 61 +++++++ 3 files changed, 300 insertions(+) create mode 100644 arch/arm/boot/dts/lan966x.dtsi create mode 100644 arch/arm/boot/dts/lan966x_pcb8291.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 235ad559acb2..2040a990f08c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -735,6 +735,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \ dtb-$(CONFIG_SOC_IMX7ULP) += \ imx7ulp-com.dtb \ imx7ulp-evk.dtb +dtb-$(CONFIG_SOC_LAN966) += \ + lan966x_pcb8291.dtb dtb-$(CONFIG_SOC_LS1021A) += \ ls1021a-moxa-uc-8410a.dtb \ ls1021a-qds.dtb \ diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi new file mode 100644 index 000000000000..6647e9ece8ae --- /dev/null +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC + * + * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries + * + * Author: Kavyasree Kotagiri + * + */ + +#include +#include +#include +#include +#include +#include + +/ { + model = "Microchip LAN966 family SoC"; + compatible = "microchip,lan966"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + clock-frequency = <600000000>; + reg = <0x0>; + }; + }; + + clocks { + sys_clk: sys_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <162500000>; + }; + + cpu_clk: cpu_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + }; + + ddr_clk: ddr_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <300000000>; + }; + + nic_clk: nic_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + }; + + clks: clock-controller@e00c00a8 { + compatible = "microchip,lan966x-gck"; + #clock-cells = <1>; + clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>; + clock-names = "cpu", "ddr", "sys"; + reg = <0xe00c00a8 0x38>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + clock-frequency = <37500000>; + arm,cpu-registers-not-fw-configured; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flx0: flexcom@e0040000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0040000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0040000 0x800>; + status = "disabled"; + }; + + flx1: flexcom@e0044000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0044000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0044000 0x800>; + status = "disabled"; + }; + + trng: rng@e0048000 { + compatible = "atmel,at91sam9g45-trng"; + reg = <0xe0048000 0x100>; + clocks = <&nic_clk>; + }; + + aes: crypto@e004c000 { + compatible = "atmel,at91sam9g46-aes"; + reg = <0xe004c000 0x100>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(13)>, + <&dma0 AT91_XDMAC_DT_PERID(12)>; + dma-names = "rx", "tx"; + clocks = <&nic_clk>; + clock-names = "aes_clk"; + }; + + flx2: flexcom@e0060000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0060000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0060000 0x800>; + status = "disabled"; + }; + + flx3: flexcom@e0064000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0064000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM3>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0064000 0x800>; + status = "disabled"; + + usart3: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + clocks = <&nic_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + }; + + dma0: dma-controller@e0068000 { + compatible = "microchip,sama7g5-dma"; + reg = <0xe0068000 0x1000>; + interrupts = ; + #dma-cells = <1>; + clocks = <&nic_clk>; + clock-names = "dma_clk"; + }; + + sha: crypto@e006c000 { + compatible = "atmel,at91sam9g46-sha"; + reg = <0xe006c000 0xec>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>; + dma-names = "tx"; + clocks = <&nic_clk>; + clock-names = "sha_clk"; + }; + + flx4: flexcom@e0070000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0070000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0070000 0x800>; + status = "disabled"; + }; + + timer0: timer@e008c000 { + compatible = "snps,dw-apb-timer"; + reg = <0xe008c000 0x400>; + clocks = <&nic_clk>; + clock-names = "timer"; + interrupts = ; + }; + + watchdog: watchdog@e0090000 { + compatible = "snps,dw-wdt"; + reg = <0xe0090000 0x1000>; + interrupts = ; + clocks = <&nic_clk>; + }; + + can0: can@e081c000 { + compatible = "bosch,m_can"; + reg = <0xe081c000 0xfc>, <0x00100000 0x4000>; + reg-names = "m_can", "message_ram"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&clks GCK_ID_MCAN0>, <&clks GCK_ID_MCAN0>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&clks GCK_ID_MCAN0>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + gpio: pinctrl@e2004064 { + compatible = "microchip,lan966x-pinctrl"; + reg = <0xe2004064 0xb4>, + <0xe2010024 0x138>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 78>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + }; + + gic: interrupt-controller@e8c11000 { + compatible = "arm,gic-400", "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupts = ; + interrupt-controller; + reg = <0xe8c11000 0x1000>, + <0xe8c12000 0x2000>, + <0xe8c14000 0x2000>, + <0xe8c16000 0x2000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/lan966x_pcb8291.dts b/arch/arm/boot/dts/lan966x_pcb8291.dts new file mode 100644 index 000000000000..ccec4177990b --- /dev/null +++ b/arch/arm/boot/dts/lan966x_pcb8291.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * lan966x_pcb8291.dts - Device Tree file for PCB8291 + */ +/dts-v1/; +#include "lan966x.dtsi" + +/ { + model = "Microchip EVB - LAN9662"; + compatible = "microchip,lan9662-pcb8291", "microchip,lan9662", "microchip,lan966"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &usart3; + }; +}; + +&gpio { + fc_shrd7_pins: fc_shrd7-pins { + pins = "GPIO_49"; + function = "fc_shrd7"; + }; + + fc_shrd8_pins: fc_shrd8-pins { + pins = "GPIO_54"; + function = "fc_shrd8"; + }; + + fc3_b_pins: fcb3-spi-pins { + /* SCK, RXD, TXD */ + pins = "GPIO_51", "GPIO_52", "GPIO_53"; + function = "fc3_b"; + }; + + can0_b_pins: can0_b_pins { + /* RX, TX */ + pins = "GPIO_35", "GPIO_36"; + function = "can0_b"; + }; +}; + +&can0 { + pinctrl-0 = <&can0_b_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&flx3 { + atmel,flexcom-mode = ; + status = "okay"; + + usart3: serial@200 { + pinctrl-0 = <&fc3_b_pins>, <&fc_shrd7_pins>, <&fc_shrd8_pins>; + pinctrl-names = "default"; + status = "okay"; + }; +}; +