From patchwork Wed Feb 16 01:45:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12747833 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AA94AC433F5 for ; Wed, 16 Feb 2022 01:54:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=72ctplgAZKY0aIFCCtq5V1AAZTHQZpAptQ2Wb0P5Bdk=; b=FNTKoc2DlZc2tq Q28/uUd6hY8BFpMjg5IeDt9F8wymk0yKXYktsK0q9lJSTXyLaak9+V1tWposzmDX+VGb2Jfq5jdto ddxQ+IrRrVEO9TklU46r8+JyiNuRIZPE3LiLSVXBx6YM/9cMPg20KtzNyx4rMwCnF6+YaW76VR+Y3 bB26AEBOug2MA/UkTs/X9HyD8nl0AZv1m+dXOdeGmZFzn5991JwVzsapDZCHNan0bQKpTahqH4Tzp Sf/JvjRGCrAiAp2UXscdOYBy62huyecF+QNt+3Ezro4hVcy5ecw+EekGHwu0NspNoLWAG9c2+kGUB TePxPVXSGGpl4uoTXBXA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nK9V8-005F2X-Ml; Wed, 16 Feb 2022 01:53:02 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nK9V4-005F17-DU; Wed, 16 Feb 2022 01:52:59 +0000 X-UUID: 8214914c651a44fa92ae93fc3f698132-20220215 X-UUID: 8214914c651a44fa92ae93fc3f698132-20220215 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1966070292; Tue, 15 Feb 2022 18:52:52 -0700 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 15 Feb 2022 17:45:33 -0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Feb 2022 09:45:20 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Feb 2022 09:45:20 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , Rex-BC Chen Subject: [3/4] dt-bindings: reset: mt8186: add DSI reset bit for MMSYS Date: Wed, 16 Feb 2022 09:45:04 +0800 Message-ID: <20220216014505.28428-4-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220216014505.28428-1-rex-bc.chen@mediatek.com> References: <20220216014505.28428-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220215_175258_472394_0C41BF8D X-CRM114-Status: UNSURE ( 9.62 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add DSI software reset bit which is controlled by MMSYS for MT8186. Signed-off-by: Rex-BC Chen --- include/dt-bindings/reset/mt8186-resets.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/reset/mt8186-resets.h b/include/dt-bindings/reset/mt8186-resets.h index 36e5764e2e6c..5f850370c42c 100644 --- a/include/dt-bindings/reset/mt8186-resets.h +++ b/include/dt-bindings/reset/mt8186-resets.h @@ -30,4 +30,7 @@ #define MT8186_TOPRGU_IMG2_SW_RST 22 #define MT8186_TOPRGU_SW_RST_NUM 23 +/* MMSYS resets */ +#define MT8186_MMSYS_SW0_RST_B_DISP_DSI0 19 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8186 */