diff mbox series

[v2,7/7] arm64: dts: imx8mp-phycore-som: Set usdhc root clock for eMMC

Message ID 20220218120458.14036-8-t.remmet@phytec.de (mailing list archive)
State New, archived
Headers show
Series arm64: dts: phyCORE-i.MX8MP SoM updates | expand

Commit Message

Teresa Remmet Feb. 18, 2022, 12:04 p.m. UTC 
From: Jonas Kuenstler <j.kuenstler@phytec.de>

Set the usdhc root clock to 400MHz to be able to support
HS400/HS400ES modes for eMMC on phyCORE-i.MX8MP SoM.

Signed-off-by: Jonas Kuenstler <j.kuenstler@phytec.de>
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
---
Changes in v2:
- Updated commit message
- Added Reviewed-by tag

 arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi | 2 ++
 1 file changed, 2 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
index c471ab252a69..79b290a002c1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
@@ -197,6 +197,8 @@  rv3028: rtc@52 {
 
 /* eMMC */
 &usdhc3 {
+	assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
+	assigned-clock-rates = <400000000>;
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc3>;
 	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;