| Message ID | 20220222113924.25799-1-Hari.PrasathGE@microchip.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | 1/3] ARM: dts: at91: sama7g5: Restrict ns_sram | expand |
On 22/02/2022 17:09:22+0530, Hari Prasath wrote: > Limit the size of SRAM available for the rest of kernel via genalloc API's to > 13k. The rest of the SRAM is used by CAN controllers and hence this restriction. > Certainly not, if the can controller need the SRAM, they have to allocate it properly. > Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com> > --- > arch/arm/boot/dts/sama7g5.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi > index eddcfbf4d223..6c7012f74b10 100644 > --- a/arch/arm/boot/dts/sama7g5.dtsi > +++ b/arch/arm/boot/dts/sama7g5.dtsi > @@ -65,7 +65,7 @@ > compatible = "mmio-sram"; > #address-cells = <1>; > #size-cells = <1>; > - reg = <0x100000 0x20000>; > + reg = <0x100000 0x3400>; > ranges; > }; > > -- > 2.17.1 >
On 22/02/2022 at 21:46, Alexandre Belloni wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On 22/02/2022 17:09:22+0530, Hari Prasath wrote: >> Limit the size of SRAM available for the rest of kernel via genalloc API's to >> 13k. The rest of the SRAM is used by CAN controllers and hence this restriction. >> > > Certainly not, if the can controller need the SRAM, they have to > allocate it properly. I'm not sure that bosh mcan driver can be used with dynamic allocation of SRAM. Is it what you're thinking about? In the meantime, I'm taking the CAN patches of this series as they match what we currently do for other users of mcan driver on other SoCs. Regards, Nicolas >> Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com> >> --- >> arch/arm/boot/dts/sama7g5.dtsi | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi >> index eddcfbf4d223..6c7012f74b10 100644 >> --- a/arch/arm/boot/dts/sama7g5.dtsi >> +++ b/arch/arm/boot/dts/sama7g5.dtsi >> @@ -65,7 +65,7 @@ >> compatible = "mmio-sram"; >> #address-cells = <1>; >> #size-cells = <1>; >> - reg = <0x100000 0x20000>; >> + reg = <0x100000 0x3400>; >> ranges; >> }; >> >> -- >> 2.17.1 >> > > -- > Alexandre Belloni, co-owner and COO, Bootlin > Embedded Linux and Kernel engineering > https://bootlin.com
On 22/02/2022 at 12:39, Hari Prasath wrote: > Limit the size of SRAM available for the rest of kernel via genalloc API's to > 13k. The rest of the SRAM is used by CAN controllers and hence this restriction. > > Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Patches 2-3 taken for 5.18. Best regards, Nicolas > --- > arch/arm/boot/dts/sama7g5.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi > index eddcfbf4d223..6c7012f74b10 100644 > --- a/arch/arm/boot/dts/sama7g5.dtsi > +++ b/arch/arm/boot/dts/sama7g5.dtsi > @@ -65,7 +65,7 @@ > compatible = "mmio-sram"; > #address-cells = <1>; > #size-cells = <1>; > - reg = <0x100000 0x20000>; > + reg = <0x100000 0x3400>; > ranges; > }; >
On 24/02/2022 16:47:03+0100, Nicolas Ferre wrote: > On 22/02/2022 at 21:46, Alexandre Belloni wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > On 22/02/2022 17:09:22+0530, Hari Prasath wrote: > > > Limit the size of SRAM available for the rest of kernel via genalloc API's to > > > 13k. The rest of the SRAM is used by CAN controllers and hence this restriction. > > > > > > > Certainly not, if the can controller need the SRAM, they have to > > allocate it properly. > > I'm not sure that bosh mcan driver can be used with dynamic allocation of > SRAM. Is it what you're thinking about? > Yes, simply add a new compatible and do the allocation where necessary. IT would be just like how we have different compatible strings for every different macb integrations.
diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index eddcfbf4d223..6c7012f74b10 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -65,7 +65,7 @@ compatible = "mmio-sram"; #address-cells = <1>; #size-cells = <1>; - reg = <0x100000 0x20000>; + reg = <0x100000 0x3400>; ranges; };
Limit the size of SRAM available for the rest of kernel via genalloc API's to 13k. The rest of the SRAM is used by CAN controllers and hence this restriction. Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com> --- arch/arm/boot/dts/sama7g5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)