From patchwork Thu Feb 24 16:01:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriel FERNANDEZ X-Patchwork-Id: 12758830 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B5F43C433EF for ; Thu, 24 Feb 2022 16:04:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xVTz4CG4YLvRaWrjbJT6z81Fhvtib4y0m42PHhgdiR8=; b=au7q30Z9uvNAm6 RWK9dEJNdQuxB8wymp9s8JNrSOhf1UfcHcqFI6Rg9NbRnFwYpeS6YiKnFj2F4pQL8zcjNKT05q/Z0 lulfSQlnvTmgEsAeIY9Q3xrY2MeoJOdSgEIJ2YzvPVcbL4LVkDPvR37Eu2YeQjpk/fjj5JZJMysK4 gb4pwhtArqhgKmlZo6yXejdFhdKjK5zDtFvvu6HOLUAAsjebOeDBCKILtyCUtvkGdkStbU+Qx40N6 feHXJUMjtgazP8mrlgm/qPGwEq7YGN5+iFKx+w5IZzgUUm3P2kE6wat5nWM1Z3VxBSk4KtDSG0I3s tkWXrS6GrVbzsEPvo2gQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nNGZh-001R39-GL; Thu, 24 Feb 2022 16:02:39 +0000 Received: from mx07-00178001.pphosted.com ([185.132.182.106]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nNGZT-001Qzb-8E for linux-arm-kernel@lists.infradead.org; Thu, 24 Feb 2022 16:02:25 +0000 Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 21OFqe5j018312; Thu, 24 Feb 2022 17:02:11 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=selector1; bh=UIStS2YTt1T7LrNscNo2b+4wp8dBm8Ks5KrvwGSzTzQ=; b=NR5/kCOfpCuAicadTXf2g7fqXp50GxIiKnFwQbGmZ7GXHxUnkLpJu0ybOGIdgCk471W7 y9zQSukn5609nkYcVYYMPoUqVqv75z3a3M8jJPAyojZ+swIxBFBv2Vstvyi8kPP97MjY U2/BkmAOMPGYewHCZZfFQPnyzRzKVbMaQS9KzK/nZGLdU5GCZE6K4HTOKr9d7IPTD7zq RZArsaG1ZPOTfGZcj+j8RfWmFQalyfBx243iMoBMxx831ceqR1gSox8/eoG8aSZqMyGU TFk3ZsgqbqDrZsktnG6vQwOZTu8vAyDkzf0P7/ywNCa5s24qJmFhBJKVxZCmN4aiAHy9 Ug== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3ee7tka6vf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Feb 2022 17:02:11 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0070A10002A; Thu, 24 Feb 2022 17:02:10 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id E143622A6FC; Thu, 24 Feb 2022 17:02:10 +0100 (CET) Received: from localhost (10.75.127.51) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Thu, 24 Feb 2022 17:02:10 +0100 From: To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Gabriel Fernandez CC: , , , , Subject: [PATCH 03/13] clk: stm32mp13: add stm32_mux clock management Date: Thu, 24 Feb 2022 17:01:31 +0100 Message-ID: <20220224160141.455881-4-gabriel.fernandez@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220224160141.455881-1-gabriel.fernandez@foss.st.com> References: <20220224160141.455881-1-gabriel.fernandez@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.51] X-ClientProxiedBy: SFHDAG2NODE1.st.com (10.75.127.4) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-02-24_03,2022-02-24_01,2022-02-23_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220224_080223_662726_76AD3D36 X-CRM114-Status: GOOD ( 17.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Gabriel Fernandez Just to introduce management of a stm32 mux clock. Signed-off-by: Gabriel Fernandez --- drivers/clk/stm32/clk-stm32-core.c | 79 ++++++++++++++++++++++++++++++ drivers/clk/stm32/clk-stm32-core.h | 34 +++++++++++++ drivers/clk/stm32/clk-stm32mp13.c | 11 +++++ 3 files changed, 124 insertions(+) diff --git a/drivers/clk/stm32/clk-stm32-core.c b/drivers/clk/stm32/clk-stm32-core.c index 0fab4a5a8c66..f34659625aff 100644 --- a/drivers/clk/stm32/clk-stm32-core.c +++ b/drivers/clk/stm32/clk-stm32-core.c @@ -91,3 +91,82 @@ int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data, return 0; } + +u8 clk_stm32_get_parent_mux(void __iomem *base, + struct clk_stm32_clock_data *data, + u16 mux_id) +{ + const struct stm32_mux_cfg *mux = &data->muxes[mux_id]; + u32 mask = BIT(mux->width) - 1; + u32 val; + + val = readl(base + mux->offset) >> mux->shift; + val &= mask; + + return val; +} + +int clk_stm32_set_parent_mux(void __iomem *base, + struct clk_stm32_clock_data *data, + u16 mux_id, u8 index) +{ + const struct stm32_mux_cfg *mux = &data->muxes[mux_id]; + + u32 mask = BIT(mux->width) - 1; + u32 reg = readl(base + mux->offset); + u32 val = index << mux->shift; + + reg &= ~(mask << mux->shift); + reg |= val; + + writel(reg, base + mux->offset); + + return 0; +} + +u8 clk_stm32_mux_get_parent(struct clk_hw *hw) +{ + struct clk_stm32_mux *mux = to_clk_stm32_mux(hw); + + return clk_stm32_get_parent_mux(mux->base, mux->clock_data, mux->mux_id); +} + +int clk_stm32_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_stm32_mux *mux = to_clk_stm32_mux(hw); + unsigned long flags = 0; + + spin_lock_irqsave(mux->lock, flags); + + clk_stm32_set_parent_mux(mux->base, mux->clock_data, mux->mux_id, index); + + spin_unlock_irqrestore(mux->lock, flags); + + return 0; +} + +const struct clk_ops clk_stm32_mux_ops = { + .get_parent = clk_stm32_mux_get_parent, + .set_parent = clk_stm32_mux_set_parent, +}; + +struct clk_hw *clk_stm32_mux_register(struct device *dev, + const struct stm32_rcc_match_data *data, + void __iomem *base, + spinlock_t *lock, + const struct clock_config *cfg) +{ + struct clk_stm32_mux *mux = cfg->clock_cfg; + struct clk_hw *hw = &mux->hw; + int err; + + mux->base = base; + mux->lock = lock; + mux->clock_data = data->clock_data; + + err = clk_hw_register(dev, hw); + if (err) + return ERR_PTR(err); + + return hw; +} diff --git a/drivers/clk/stm32/clk-stm32-core.h b/drivers/clk/stm32/clk-stm32-core.h index 519723ae97eb..7c9f503d3388 100644 --- a/drivers/clk/stm32/clk-stm32-core.h +++ b/drivers/clk/stm32/clk-stm32-core.h @@ -83,10 +83,44 @@ int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data, /* DIV define */ #define DIV_NO_RDY 0xFF +/* Definition of clock structure */ +struct clk_stm32_mux { + u16 mux_id; + struct clk_hw hw; + void __iomem *base; + struct clk_stm32_clock_data *clock_data; + spinlock_t *lock; /* spin lock */ +}; + +#define to_clk_stm32_mux(_hw) container_of(_hw, struct clk_stm32_mux, hw) + +/* Clock ops */ +u8 clk_stm32_get_parent_mux(void __iomem *base, + struct clk_stm32_clock_data *data, u16 mux_id); + +int clk_stm32_set_parent_mux(void __iomem *base, + struct clk_stm32_clock_data *data, u16 mux_id, + u8 index); + +u8 clk_stm32_mux_get_parent(struct clk_hw *hw); +int clk_stm32_mux_set_parent(struct clk_hw *hw, u8 index); + +extern const struct clk_ops clk_stm32_mux_ops; + /* Clock registering */ +struct clk_hw *clk_stm32_mux_register(struct device *dev, + const struct stm32_rcc_match_data *data, + void __iomem *base, + spinlock_t *lock, + const struct clock_config *cfg); + #define STM32_CLOCK_CFG(_binding, _clk, _struct, _register)\ {\ .id = (_binding),\ .clock_cfg = (_struct) {_clk},\ .func = (_register),\ } + +#define STM32_MUX_CFG(_binding, _clk)\ + STM32_CLOCK_CFG(_binding, &(_clk), struct clk_stm32_mux *,\ + &clk_stm32_mux_register) diff --git a/drivers/clk/stm32/clk-stm32mp13.c b/drivers/clk/stm32/clk-stm32mp13.c index 6908c2fcd594..89d4e039e4e6 100644 --- a/drivers/clk/stm32/clk-stm32mp13.c +++ b/drivers/clk/stm32/clk-stm32mp13.c @@ -400,7 +400,18 @@ static const struct stm32_mux_cfg stm32mp13_muxes[] = { CFG_MUX(MUX_SDMMC2, RCC_SDMMC12CKSELR, 3, 3), }; +static const char * const eth12_src[] = { + "pll4_p", "pll3_q" +}; + +static struct clk_stm32_mux ck_ker_eth1 = { + .mux_id = MUX_ETH1, + .hw.init = CLK_HW_INIT_PARENTS("ck_ker_eth1", eth12_src, &clk_stm32_mux_ops, + CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), +}; + static const struct clock_config stm32mp13_clock_cfg[] = { + STM32_MUX_CFG(NO_ID, ck_ker_eth1), }; u16 stm32mp13_cpt_gate[GATE_NB];