From patchwork Thu Feb 24 16:01:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriel FERNANDEZ X-Patchwork-Id: 12758833 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4DE67C433EF for ; Thu, 24 Feb 2022 16:05:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ZVvtz0kNPiOFgf3LBM3d3OGZRSSG21DvTdsOpBJUlZE=; b=ALE2+tZ0HWvvVk ZhwgisUFaMMXgx04aM3n27ucn5FoHC4hdnzZMMFNmYut4pPsO6BZLm2Vv5JYpsIIYDEBGf7U3sCqJ snJTO3tUwV60Pq8gdGygZT2hDyz80GrJBj/zsxxOBS4gLdcklNnltk2ovFQBNujEylr5qPQ6Qk/Ho P7UNgiv3xPUNl6ydfZDsYEAkseNG90qhtZq+2lakOD55wiveeaYwITxB8Ik7Lm7PdMcstaXrpmg5L zomaGhi0rFnkkCsUpvYehMADK7vQI2JMmQveddNdkHABJlL+MVea2rqXPdDJ52DCDBDPNuIBRNWyR tZN0dnO6vUl3RROD5Z1w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nNGap-001RVU-So; Thu, 24 Feb 2022 16:03:48 +0000 Received: from mx08-00178001.pphosted.com ([91.207.212.93] helo=mx07-00178001.pphosted.com) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nNGZU-001QyX-18 for linux-arm-kernel@lists.infradead.org; Thu, 24 Feb 2022 16:02:29 +0000 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 21OCQjPN032631; Thu, 24 Feb 2022 17:02:14 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=selector1; bh=hNd85QuxAPt1JKcUQ6LwOsIx66UTxc4JQbMHzAv5lJo=; b=08/v4qE07WAeCPZLPomUgzvVJaI154SLuO2w6YT/Jt39YIFsxsDa1QaPvBy1puhqYv8Q bAZasbL/IKmKo+QOldo6NgeMLATYkIa8XRWHh9tcLDw4PDcaUSG322yQb/1aO+uHmYdB JYSNj9NL67eDufoUtEt25RSLw0X4nSfi958TRJlqo0c2MX0dndaVHDG4V+k/VJQBSW/y FPNpg0zTLIigs0puaON40K7PpjHWq12+M8e85a1HgEdXgYdAw8FuLiyxnvqEdR56+VCI 9egs3B3HU3QNNmQx319j8HPojzsDx4wwvxIz1l4qLH4YfqSqCdPjyb7qaM//0gYs2PCh gw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3ee5x0369f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Feb 2022 17:02:14 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 037E8100034; Thu, 24 Feb 2022 17:02:13 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id E6AE822A6FC; Thu, 24 Feb 2022 17:02:12 +0100 (CET) Received: from localhost (10.75.127.48) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Thu, 24 Feb 2022 17:02:12 +0100 From: To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Gabriel Fernandez CC: , , , , Subject: [PATCH 06/13] clk: stm32mp13: add composite clock Date: Thu, 24 Feb 2022 17:01:34 +0100 Message-ID: <20220224160141.455881-7-gabriel.fernandez@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220224160141.455881-1-gabriel.fernandez@foss.st.com> References: <20220224160141.455881-1-gabriel.fernandez@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.48] X-ClientProxiedBy: SFHDAG2NODE3.st.com (10.75.127.6) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-02-24_03,2022-02-24_01,2022-02-23_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220224_080224_434160_93E51B4A X-CRM114-Status: GOOD ( 20.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Gabriel Fernandez Just to introduce management of stm32 composite clock. Signed-off-by: Gabriel Fernandez --- drivers/clk/stm32/clk-stm32-core.c | 181 +++++++++++++++++++++++++++++ drivers/clk/stm32/clk-stm32-core.h | 33 ++++++ drivers/clk/stm32/clk-stm32mp13.c | 28 +++++ 3 files changed, 242 insertions(+) diff --git a/drivers/clk/stm32/clk-stm32-core.c b/drivers/clk/stm32/clk-stm32-core.c index 57d039168779..3b00918d0753 100644 --- a/drivers/clk/stm32/clk-stm32-core.c +++ b/drivers/clk/stm32/clk-stm32-core.c @@ -393,6 +393,166 @@ const struct clk_ops clk_stm32_mux_ops = { .set_parent = clk_stm32_mux_set_parent, }; +int clk_stm32_composite_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_stm32_composite *composite = to_clk_stm32_composite(hw); + unsigned long flags = 0; + int ret; + + if (composite->div_id == NO_STM32_DIV) + return rate; + + spin_lock_irqsave(composite->lock, flags); + + ret = clk_stm32_set_rate_divider(composite->base, composite->clock_data, + composite->div_id, rate, parent_rate); + + spin_unlock_irqrestore(composite->lock, flags); + + return ret; +} + +unsigned long clk_stm32_composite_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_stm32_composite *composite = to_clk_stm32_composite(hw); + + if (composite->div_id == NO_STM32_DIV) + return parent_rate; + + return clk_stm32_get_rate_divider(composite->base, + composite->clock_data, + composite->div_id, + parent_rate); +} + +long clk_stm32_composite_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_stm32_composite *composite = to_clk_stm32_composite(hw); + + const struct stm32_div_cfg *divider; + + if (composite->div_id == NO_STM32_DIV) + return rate; + + divider = &composite->clock_data->dividers[composite->div_id]; + + /* if read only, just return current value */ + if (divider->flags & CLK_DIVIDER_READ_ONLY) { + u32 val; + + val = readl(composite->base + divider->offset) >> divider->shift; + val &= clk_div_mask(divider->width); + + return divider_ro_round_rate(hw, rate, prate, divider->table, + divider->width, divider->flags, + val); + } + + return divider_round_rate_parent(hw, clk_hw_get_parent(hw), + rate, prate, divider->table, + divider->width, divider->flags); +} + +u8 clk_stm32_composite_get_parent(struct clk_hw *hw) +{ + struct clk_stm32_composite *composite = to_clk_stm32_composite(hw); + + return clk_stm32_get_parent_mux(composite->base, composite->clock_data, + composite->mux_id); +} + +int clk_stm32_composite_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_stm32_composite *composite = to_clk_stm32_composite(hw); + unsigned long flags = 0; + + spin_lock_irqsave(composite->lock, flags); + + clk_stm32_set_parent_mux(composite->base, composite->clock_data, + composite->mux_id, index); + + spin_unlock_irqrestore(composite->lock, flags); + + return 0; +} + +void clk_stm32_composite_gate_endisable(struct clk_hw *hw, int enable) +{ + struct clk_stm32_composite *composite = to_clk_stm32_composite(hw); + unsigned long flags = 0; + + spin_lock_irqsave(composite->lock, flags); + + clk_stm32_endisable_gate(composite->base, composite->clock_data, + composite->gate_id, enable); + + spin_unlock_irqrestore(composite->lock, flags); +} + +int clk_stm32_composite_gate_enable(struct clk_hw *hw) +{ + struct clk_stm32_composite *composite = to_clk_stm32_composite(hw); + + if (composite->gate_id == NO_STM32_GATE) + return 0; + + clk_stm32_composite_gate_endisable(hw, 1); + + return 0; +} + +void clk_stm32_composite_gate_disable(struct clk_hw *hw) +{ + struct clk_stm32_composite *composite = to_clk_stm32_composite(hw); + + if (composite->gate_id == NO_STM32_GATE) + return; + + clk_stm32_composite_gate_endisable(hw, 0); +} + +int clk_stm32_composite_is_enabled(struct clk_hw *hw) +{ + struct clk_stm32_composite *composite = to_clk_stm32_composite(hw); + + if (composite->gate_id == NO_STM32_GATE) + return (__clk_get_enable_count(hw->clk) > 0); + + return clk_stm32_is_enabled_gate(composite->base, composite->clock_data, + composite->gate_id); +} + +static void clk_stm32_composite_disable_unused(struct clk_hw *hw) +{ + struct clk_stm32_composite *composite = to_clk_stm32_composite(hw); + unsigned long flags = 0; + + if (composite->gate_id == NO_STM32_GATE) + return; + + spin_lock_irqsave(composite->lock, flags); + + clk_stm32_disable_unused_gate(composite->base, composite->clock_data, + composite->gate_id); + + spin_unlock_irqrestore(composite->lock, flags); +} + +const struct clk_ops clk_stm32_composite_ops = { + .set_rate = clk_stm32_composite_set_rate, + .recalc_rate = clk_stm32_composite_recalc_rate, + .round_rate = clk_stm32_composite_round_rate, + .get_parent = clk_stm32_composite_get_parent, + .set_parent = clk_stm32_composite_set_parent, + .enable = clk_stm32_composite_gate_enable, + .disable = clk_stm32_composite_gate_disable, + .is_enabled = clk_stm32_composite_is_enabled, + .disable_unused = clk_stm32_composite_disable_unused, +}; + struct clk_hw *clk_stm32_gate_register(struct device *dev, const struct stm32_rcc_match_data *data, void __iomem *base, @@ -455,3 +615,24 @@ struct clk_hw *clk_stm32_mux_register(struct device *dev, return hw; } + +struct clk_hw *clk_stm32_composite_register(struct device *dev, + const struct stm32_rcc_match_data *data, + void __iomem *base, + spinlock_t *lock, + const struct clock_config *cfg) +{ + struct clk_stm32_composite *composite = cfg->clock_cfg; + struct clk_hw *hw = &composite->hw; + int err; + + composite->base = base; + composite->lock = lock; + composite->clock_data = data->clock_data; + + err = clk_hw_register(dev, hw); + if (err) + return ERR_PTR(err); + + return hw; +} diff --git a/drivers/clk/stm32/clk-stm32-core.h b/drivers/clk/stm32/clk-stm32-core.h index 833a3d4a064f..846d063ecc6f 100644 --- a/drivers/clk/stm32/clk-stm32-core.h +++ b/drivers/clk/stm32/clk-stm32-core.h @@ -114,6 +114,18 @@ struct clk_stm32_mux { #define to_clk_stm32_mux(_hw) container_of(_hw, struct clk_stm32_mux, hw) +struct clk_stm32_composite { + u16 gate_id; + u16 mux_id; + u16 div_id; + struct clk_hw hw; + void __iomem *base; + struct clk_stm32_clock_data *clock_data; + spinlock_t *lock; /* spin lock */ +}; + +#define to_clk_stm32_composite(_hw) container_of(_hw, struct clk_stm32_composite, hw) + /* Clock ops */ void clk_stm32_endisable_gate(void __iomem *base, struct clk_stm32_clock_data *data, @@ -156,9 +168,20 @@ int clk_stm32_set_parent_mux(void __iomem *base, u8 clk_stm32_mux_get_parent(struct clk_hw *hw); int clk_stm32_mux_set_parent(struct clk_hw *hw, u8 index); +void clk_stm32_composite_gate_endisable(struct clk_hw *hw, int enable); +int clk_stm32_composite_gate_enable(struct clk_hw *hw); +void clk_stm32_composite_gate_disable(struct clk_hw *hw); +int clk_stm32_composite_is_enabled(struct clk_hw *hw); +u8 clk_stm32_composite_get_parent(struct clk_hw *hw); +int clk_stm32_composite_set_parent(struct clk_hw *hw, u8 index); +unsigned long clk_stm32_composite_recalc_rate(struct clk_hw *hw, unsigned long parent_rate); +long clk_stm32_composite_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate); +int clk_stm32_composite_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate); + extern const struct clk_ops clk_stm32_gate_ops; extern const struct clk_ops clk_stm32_divider_ops; extern const struct clk_ops clk_stm32_mux_ops; +extern const struct clk_ops clk_stm32_composite_ops; /* Clock registering */ struct clk_hw *clk_stm32_gate_register(struct device *dev, @@ -179,6 +202,12 @@ struct clk_hw *clk_stm32_mux_register(struct device *dev, spinlock_t *lock, const struct clock_config *cfg); +struct clk_hw *clk_stm32_composite_register(struct device *dev, + const struct stm32_rcc_match_data *data, + void __iomem *base, + spinlock_t *lock, + const struct clock_config *cfg); + #define STM32_CLOCK_CFG(_binding, _clk, _struct, _register)\ {\ .id = (_binding),\ @@ -197,3 +226,7 @@ struct clk_hw *clk_stm32_mux_register(struct device *dev, #define STM32_MUX_CFG(_binding, _clk)\ STM32_CLOCK_CFG(_binding, &(_clk), struct clk_stm32_mux *,\ &clk_stm32_mux_register) + +#define STM32_COMPOSITE_CFG(_binding, _clk)\ + STM32_CLOCK_CFG(_binding, &(_clk), struct clk_stm32_composite *,\ + &clk_stm32_composite_register) diff --git a/drivers/clk/stm32/clk-stm32mp13.c b/drivers/clk/stm32/clk-stm32mp13.c index 66ebfe810b08..1b27c5d4b97d 100644 --- a/drivers/clk/stm32/clk-stm32mp13.c +++ b/drivers/clk/stm32/clk-stm32mp13.c @@ -404,6 +404,14 @@ static const char * const eth12_src[] = { "pll4_p", "pll3_q" }; +static const char * const mco1_src[] = { + "ck_hsi", "ck_hse", "ck_csi", "ck_lsi", "ck_lse" +}; + +static const char * const mco2_src[] = { + "ck_mpu", "ck_axi", "ck_mlahb", "pll4_p", "ck_hse", "ck_hsi" +}; + static struct clk_stm32_mux ck_ker_eth1 = { .mux_id = MUX_ETH1, .hw.init = CLK_HW_INIT_PARENTS("ck_ker_eth1", eth12_src, &clk_stm32_mux_ops, @@ -421,10 +429,30 @@ static struct clk_stm32_div eth1ptp_k = { CLK_SET_RATE_NO_REPARENT), }; +static struct clk_stm32_composite ck_mco1 = { + .gate_id = GATE_MCO1, + .mux_id = MUX_MCO1, + .div_id = DIV_MCO1, + .hw.init = CLK_HW_INIT_PARENTS("ck_mco1", mco1_src, &clk_stm32_composite_ops, + CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT | + CLK_IGNORE_UNUSED), +}; + +static struct clk_stm32_composite ck_mco2 = { + .gate_id = GATE_MCO2, + .mux_id = MUX_MCO2, + .div_id = DIV_MCO2, + .hw.init = CLK_HW_INIT_PARENTS("ck_mco2", mco2_src, &clk_stm32_composite_ops, + CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT | + CLK_IGNORE_UNUSED), +}; + static const struct clock_config stm32mp13_clock_cfg[] = { STM32_MUX_CFG(NO_ID, ck_ker_eth1), STM32_GATE_CFG(ETH1CK_K, eth1ck_k), STM32_DIV_CFG(ETH1PTP_K, eth1ptp_k), + STM32_COMPOSITE_CFG(CK_MCO1, ck_mco1), + STM32_COMPOSITE_CFG(CK_MCO2, ck_mco2), }; u16 stm32mp13_cpt_gate[GATE_NB];