| Message ID | 20220225090002.2497057-3-peng.fan@oss.nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | imx: add hdmi 27m phy clk | expand |
On 22-02-25 17:00:02, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@nxp.com> > > According to pll documentation, the 3rd pll ref clock should be > hdmi phy 27m clock, not dummy clock. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> > --- > drivers/clk/imx/clk-imx8mq.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c > index 83cc2b1c3294..a9e69b6355ed 100644 > --- a/drivers/clk/imx/clk-imx8mq.c > +++ b/drivers/clk/imx/clk-imx8mq.c > @@ -25,7 +25,7 @@ static u32 share_count_sai6; > static u32 share_count_dcss; > static u32 share_count_nand; > > -static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy", "dummy", }; > +static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "hdmi_phy_27m", "dummy", }; > static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; > static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; > static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", }; > -- > 2.25.1 >
On 22-02-25 17:00:02, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@nxp.com> > > According to pll documentation, the 3rd pll ref clock should be > hdmi phy 27m clock, not dummy clock. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> Applied, thanks! > --- > drivers/clk/imx/clk-imx8mq.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c > index 83cc2b1c3294..a9e69b6355ed 100644 > --- a/drivers/clk/imx/clk-imx8mq.c > +++ b/drivers/clk/imx/clk-imx8mq.c > @@ -25,7 +25,7 @@ static u32 share_count_sai6; > static u32 share_count_dcss; > static u32 share_count_nand; > > -static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy", "dummy", }; > +static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "hdmi_phy_27m", "dummy", }; > static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; > static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; > static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", }; > -- > 2.25.1 >
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index 83cc2b1c3294..a9e69b6355ed 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -25,7 +25,7 @@ static u32 share_count_sai6; static u32 share_count_dcss; static u32 share_count_nand; -static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy", "dummy", }; +static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "hdmi_phy_27m", "dummy", }; static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };