From patchwork Fri Feb 25 13:31:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriel FERNANDEZ X-Patchwork-Id: 12760351 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3B444C433EF for ; Fri, 25 Feb 2022 13:44:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=sWjxQmXfi+3MDUJ7vgu/9F4SZLtvlN7XbF1LzXw+XI4=; b=Q/yKyKpKtIl6XG j4KAXOA1dtF1j5/+xoSHbPi3SEBD+ntx8/8snpGsb1r9Zgs479skrvHzTUOs+Kxkgyiu3Cs00kA1D O21ebwkaVhU81UdXI0h9gZQfzUs6lfZOii0Znjn2sSqh+jP1Yb7+UtL6B0WFA3G5vnvfD0JHiE+kw CJS4HAoO+XuCnfpBrRYCpAsrxdXvaxBiAadMJG5kUGrgwFzitDUveJmqXAxpsF1mG2JnCUlXOhMK7 ofsLE8dUstrcNhZCPEswFtecMiBDaI0J4LDEBhJf5bRa+qFN/jJiUG68KQhxAuHofCwCQh4zMQazZ dJndo/KetAAG93Fv3MjA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nNarl-005C2e-P7; Fri, 25 Feb 2022 13:42:38 +0000 Received: from mx07-00178001.pphosted.com ([185.132.182.106]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nNajj-0058dD-NV for linux-arm-kernel@lists.infradead.org; Fri, 25 Feb 2022 13:34:21 +0000 Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 21P9a5LH019229; Fri, 25 Feb 2022 14:34:14 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=selector1; bh=TT2fZVNlHK9vb5NNbFYqvqP0J/vHa5Erb6Q7BQphl7M=; b=yITRAYpl4ESTtL+rBulsalsdd/+Jh54n1doKEQB39eSbUV76vNn5o4+slbanGzyaggjp I4MtsNbuRveHgcGQ5d3RfT0yV0cKSaX6Lfy/TRNWju5FEocnVMn+TceNOeAdQyZBeMK6 Vf8KhRwCzXnOAjIb2yOZOEDYtfOZ5RYKsPDg2SvxbUw3o6k7kdklzXaSt8r0BINrc35Q 6DiZ+RpyG9qv/d7Z3maZMlvxEUW482T3aY90CNsnOe0GMwNLhP/FWo5J0xwzwa31nqAm blyj4eQ/lW9IhZ7PfU8LMPWKv6J/zgFLNiuXp2Vh4/9s+aI3aPDwBjUm3mUaxHV9l0kd LQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3eevmgsa1e-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Feb 2022 14:34:14 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id F378A10002A; Fri, 25 Feb 2022 14:34:13 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id EB9582278AA; Fri, 25 Feb 2022 14:34:13 +0100 (CET) Received: from localhost (10.75.127.47) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Fri, 25 Feb 2022 14:34:13 +0100 From: To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Gabriel Fernandez CC: , , , , Subject: [PATCH v2 10/13] clk: stm32mp13: add multi mux function Date: Fri, 25 Feb 2022 14:31:34 +0100 Message-ID: <20220225133137.813919-11-gabriel.fernandez@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220225133137.813919-1-gabriel.fernandez@foss.st.com> References: <20220225133137.813919-1-gabriel.fernandez@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-02-25_08,2022-02-25_01,2022-02-23_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220225_053420_128932_31E3DAA4 X-CRM114-Status: GOOD ( 18.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Gabriel Fernandez Some RCC muxes can manages two output clocks with same register. Signed-off-by: Gabriel Fernandez --- drivers/clk/stm32/clk-stm32-core.c | 10 ++++++++++ drivers/clk/stm32/clk-stm32-core.h | 2 ++ drivers/clk/stm32/clk-stm32mp13.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 42 insertions(+) diff --git a/drivers/clk/stm32/clk-stm32-core.c b/drivers/clk/stm32/clk-stm32-core.c index fc32e62e0b44..69cfa2d1b8e2 100644 --- a/drivers/clk/stm32/clk-stm32-core.c +++ b/drivers/clk/stm32/clk-stm32-core.c @@ -480,6 +480,16 @@ int clk_stm32_composite_set_parent(struct clk_hw *hw, u8 index) spin_unlock_irqrestore(composite->lock, flags); + if (composite->clock_data->is_multi_mux) { + struct clk_hw *other_mux_hw = composite->clock_data->is_multi_mux(hw); + + if (other_mux_hw) { + struct clk_hw *hwp = clk_hw_get_parent_by_index(hw, index); + + clk_hw_reparent(other_mux_hw, hwp); + } + } + return 0; } diff --git a/drivers/clk/stm32/clk-stm32-core.h b/drivers/clk/stm32/clk-stm32-core.h index 8ffa700323b8..61a7b4bb6a19 100644 --- a/drivers/clk/stm32/clk-stm32-core.h +++ b/drivers/clk/stm32/clk-stm32-core.h @@ -61,6 +61,7 @@ struct clk_stm32_clock_data { const struct stm32_gate_cfg *gates; const struct stm32_mux_cfg *muxes; const struct stm32_div_cfg *dividers; + struct clk_hw *(*is_multi_mux)(struct clk_hw *hw); }; struct stm32_rcc_match_data { @@ -72,6 +73,7 @@ struct stm32_rcc_match_data { u32 clear_offset; int (*check_security)(void __iomem *base, const struct clock_config *cfg); + int (*multi_mux)(void __iomem *base, const struct clock_config *cfg); }; int stm32_rcc_reset_init(struct device *dev, const struct of_device_id *match, diff --git a/drivers/clk/stm32/clk-stm32mp13.c b/drivers/clk/stm32/clk-stm32mp13.c index 462e00877474..783a54e08439 100644 --- a/drivers/clk/stm32/clk-stm32mp13.c +++ b/drivers/clk/stm32/clk-stm32mp13.c @@ -1429,6 +1429,35 @@ static int stm32mp13_clock_is_provided_by_secure(void __iomem *base, return 0; } +struct multi_mux { + struct clk_hw *hw1; + struct clk_hw *hw2; +}; + +static struct multi_mux *stm32_mp13_multi_mux[MUX_NB] = { + [MUX_SPI23] = &(struct multi_mux){ &spi2_k.hw, &spi3_k.hw }, + [MUX_I2C12] = &(struct multi_mux){ &i2c1_k.hw, &i2c2_k.hw }, + [MUX_LPTIM45] = &(struct multi_mux){ &lptim4_k.hw, &lptim5_k.hw }, + [MUX_UART35] = &(struct multi_mux){ &usart3_k.hw, &uart5_k.hw }, + [MUX_UART78] = &(struct multi_mux){ &uart7_k.hw, &uart8_k.hw }, + [MUX_SAI1] = &(struct multi_mux){ &sai1_k.hw, &adfsdm_k.hw }, +}; + +static struct clk_hw *stm32mp13_is_multi_mux(struct clk_hw *hw) +{ + struct clk_stm32_composite *composite = to_clk_stm32_composite(hw); + struct multi_mux *mmux = stm32_mp13_multi_mux[composite->mux_id]; + + if (mmux) { + if (!(mmux->hw1 == hw)) + return mmux->hw1; + else + return mmux->hw2; + } + + return NULL; +} + u16 stm32mp13_cpt_gate[GATE_NB]; struct clk_stm32_clock_data stm32mp13_clock_data = { @@ -1436,6 +1465,7 @@ struct clk_stm32_clock_data stm32mp13_clock_data = { .gates = stm32mp13_gates, .muxes = stm32mp13_muxes, .dividers = stm32mp13_dividers, + .is_multi_mux = stm32mp13_is_multi_mux, }; static const struct stm32_rcc_match_data stm32mp13_data = {