From patchwork Mon Feb 28 11:19:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12763105 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 92400C433F5 for ; Mon, 28 Feb 2022 11:55:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=SCqt4NEeEkzFxhsw6cNwTa3T/nCJDYFC9BL1YbayQYc=; b=dwx5hnYqpS+sPp 9Ovo2kNZbFzt1jtRAf7KbELWs4nTaqtknKLa6+VQElJSF3gFVaqbl9LQElXq42CtjsE7ucHbWT0Tu 9ehOvpngb5FWtRxyk7DkQb8T1ttD7fcsYkwjSsxn/allvR6jvMpVgemqgW4CIqGm6eoHfIIq59A5o tUrU4wfddbySVaMADaHxR1yK1CUYsCkTXyfl1IGrq7v4ojA2u5fGVS8ej5IaXGYB0GkufyPkNUJU4 5FtKCS6W97LyyrX4iQ4iG8yRhXyxbdPZLib8I7Hg7Ude+4No73Gyg5acmVcc06ukg6N/twe+nvb95 sUcpS9jEKT2WSaap11AQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nOeaq-00C0JY-68; Mon, 28 Feb 2022 11:53:32 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nOe32-00BnaE-Pa for linux-arm-kernel@lists.infradead.org; Mon, 28 Feb 2022 11:18:38 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646047116; x=1677583116; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DN+94+J4jdsioJx8FJjTB5GVluUzTVOxlq0TAtH+lSY=; b=pq0QSH9zQkVEQ65LVLGYt7yeEOYWjq1Stg+ZXMxgypXtKATtqFc7ko64 h91mHYpxr9vn7mIjpOcfe+3caPaVQQxJZB9+mI3MWOsEWAlNLRRXflv8R NQ4wk8Cqq6a510aNzMNl/phycPDD1BLMul913rUc/g6a//TLwci3JMvMe 242PLylE0+X/vf2l7iI29UBVLGrKXkTvNBeMtSVSKdeZC4j5JOW2ncm/4 zpdV9dV266U3q+VOjPRUSCCu4eQRp2Bv95E8BIDSPtJ50WxafxbTKyatL kSWGVEBz0CIMss9VDpxfPXWdVuaNZARfwIqyAwtNY8OkzNWxx+OvuQLn6 A==; X-IronPort-AV: E=Sophos;i="5.90,142,1643698800"; d="scan'208";a="163859419" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Feb 2022 04:18:35 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 28 Feb 2022 04:18:35 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 28 Feb 2022 04:18:33 -0700 From: Claudiu Beznea To: , CC: , , Claudiu Beznea Subject: [PATCH 7/7] clocksource/drivers/timer-microchip-pit64b: use mchp_pit64b_{suspend, resume} Date: Mon, 28 Feb 2022 13:19:23 +0200 Message-ID: <20220228111923.1400049-8-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220228111923.1400049-1-claudiu.beznea@microchip.com> References: <20220228111923.1400049-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220228_031836_951260_60CC86FC X-CRM114-Status: GOOD ( 10.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Use mchp_pit64b_suspend() and mchp_pit64b_resume() to disable or enable timers clocks on init and remove specific clk_prepare_{disable, enable} calls. This is ok also for clockevent timer as proper clock enable, disable is done on .set_state_oneshot, .set_state_periodic, .set_state_shutdown calls. Signed-off-by: Claudiu Beznea Reported-by: kernel test robot --- drivers/clocksource/timer-microchip-pit64b.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/drivers/clocksource/timer-microchip-pit64b.c b/drivers/clocksource/timer-microchip-pit64b.c index dd1661604966..0f0d8160660c 100644 --- a/drivers/clocksource/timer-microchip-pit64b.c +++ b/drivers/clocksource/timer-microchip-pit64b.c @@ -352,6 +352,7 @@ static int __init mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer, if (!cs) return -ENOMEM; + mchp_pit64b_resume(timer); mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0); mchp_pit64b_cs_base = timer->base; @@ -373,8 +374,7 @@ static int __init mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer, pr_debug("clksrc: Failed to register PIT64B clocksource!\n"); /* Stop timer. */ - writel_relaxed(MCHP_PIT64B_CR_SWRST, - timer->base + MCHP_PIT64B_CR); + mchp_pit64b_suspend(timer); kfree(cs); return ret; @@ -462,19 +462,10 @@ static int __init mchp_pit64b_dt_init_timer(struct device_node *node, if (ret) goto irq_unmap; - ret = clk_prepare_enable(timer.pclk); - if (ret) - goto irq_unmap; - - if (timer.mode & MCHP_PIT64B_MR_SGCLK) { - ret = clk_prepare_enable(timer.gclk); - if (ret) - goto pclk_unprepare; - + if (timer.mode & MCHP_PIT64B_MR_SGCLK) clk_rate = clk_get_rate(timer.gclk); - } else { + else clk_rate = clk_get_rate(timer.pclk); - } clk_rate = clk_rate / (MCHP_PIT64B_MODE_TO_PRES(timer.mode) + 1); if (clkevt)