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[1/2] ARM: dts: at91: sama7g5: add eic node

Message ID 20220228122326.1400954-2-claudiu.beznea@microchip.com (mailing list archive)
State New, archived
Headers show
Series ARM: at91: enable eic | expand

Commit Message

Claudiu Beznea Feb. 28, 2022, 12:23 p.m. UTC 
Add EIC node.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/boot/dts/sama7g5.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

Comments

Nicolas Ferre March 4, 2022, 10:42 a.m. UTC | #1 
On 28/02/2022 at 13:23, Claudiu Beznea wrote:
> Add EIC node.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>

Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>

Queued in at91-dt for 5.18.
Best regards,
   Nicolas

> ---
>   arch/arm/boot/dts/sama7g5.dtsi | 13 +++++++++++++
>   1 file changed, 13 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
> index e6d0c90cf710..efc5437f09ec 100644
> --- a/arch/arm/boot/dts/sama7g5.dtsi
> +++ b/arch/arm/boot/dts/sama7g5.dtsi
> @@ -455,6 +455,19 @@ i2s1: i2s@e1620000 {
>   			status = "disabled";
>   		};
>   
> +		eic: interrupt-controller@e1628000 {
> +			compatible = "microchip,sama7g5-eic";
> +			reg = <0xe1628000 0xec>;
> +			interrupt-parent = <&gic>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
> +			clock-names = "pclk";
> +			status = "disabled";
> +		};
> +
>   		pit64b0: timer@e1800000 {
>   			compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b";
>   			reg = <0xe1800000 0x4000>;
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
index e6d0c90cf710..efc5437f09ec 100644
--- a/arch/arm/boot/dts/sama7g5.dtsi
+++ b/arch/arm/boot/dts/sama7g5.dtsi
@@ -455,6 +455,19 @@  i2s1: i2s@e1620000 {
 			status = "disabled";
 		};
 
+		eic: interrupt-controller@e1628000 {
+			compatible = "microchip,sama7g5-eic";
+			reg = <0xe1628000 0xec>;
+			interrupt-parent = <&gic>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
 		pit64b0: timer@e1800000 {
 			compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b";
 			reg = <0xe1800000 0x4000>;