From patchwork Thu Mar 3 14:06:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12767549 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1341AC433F5 for ; Thu, 3 Mar 2022 14:14:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2G4XEFQ5DwC2YIvKDf8be3Vdp5NzWS1hNNHk++kQCeE=; b=GgpL4QDbl6ZOFW 2HF/eESvsF/jkhxxvnp5KHQ/v9qOjFnfGv4Mn7eBMiPQD7XRC2i/YRzKA7mo0QOjxfyS9q145inq5 KGcrvnU0a8nyAtzgSarGpVMEiA8QY8aVHO/sVFbAqXI/NDFdGmsUP1qCVUQns558maFtUJL7razr0 iDD8z0MGSItIEpYMnsxeA1QKPfmKRUzRC1O6AVXq3nDtETs+mnrtM9YNLQB82bg1fmMlcrSqY34aN wI6T2MHwRUxQAU+gJyJxI1LDFPJ4n7bo9n4r6hF9aYWMSUEgNtjfb/Q8wjanMTetU33bjOsrMqjxw UyY4knTTwEwN9S3BdtgQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nPmCT-006ZvX-Jq; Thu, 03 Mar 2022 14:13:01 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nPmCL-006Zrm-Bv for linux-arm-kernel@lists.infradead.org; Thu, 03 Mar 2022 14:12:55 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646316773; x=1677852773; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ii1IDpzBCywstrqs0ihtCZsjxQTenixL/7CD9yqjDzk=; b=0IJkRaYFQ/844HdRqB61/ab3AYjH3bfB7/e/j/ucrZeb1Z8CCqsBZ2sh 6gMzohKnBixuCz3P4WJ17zgRc0dbI7xHDlWA/r8r/1iYyucjHJoi5EsB0 SZ0dfq8D+KE18wfYHfu77UT1ZoouUVYGcdlXGfmNeK1V/KYKekLrKtES6 XH0xEodoroq7V8s4vGoa5C8ojPqrPcx0XPl1jxwc9cn8+RiDsmonhjEO9 YzANjPrioefLETWGwiZ1d0mks44Pp7eksUMEOt0SX0sACSQrI4FgRjmkV 70lL8FPf9LVQN1NgqBhOwEWlOL7NWgmGAe1r6+wFZWezXxjeMzNNTol21 g==; X-IronPort-AV: E=Sophos;i="5.90,151,1643698800"; d="scan'208";a="155125685" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 Mar 2022 07:12:53 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 3 Mar 2022 07:12:52 -0700 Received: from ROB-ULT-M68701.amer.actel.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 3 Mar 2022 07:12:46 -0700 From: Sergiu Moga To: , , , , , CC: , , , , Sergiu Moga Subject: [PATCH v2 4/5] dt-bindings: rtc: convert at91sam9 bindings to json-schema Date: Thu, 3 Mar 2022 16:06:25 +0200 Message-ID: <20220303140626.38129-5-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303140626.38129-1-sergiu.moga@microchip.com> References: <20220303140626.38129-1-sergiu.moga@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220303_061253_456004_06EDC207 X-CRM114-Status: GOOD ( 16.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert RTC binding for Atmel/Microchip SoCs to Device Tree Schema format. Signed-off-by: Sergiu Moga --- .../bindings/rtc/atmel,at91sam9-rtc.txt | 25 -------- .../bindings/rtc/atmel,at91sam9-rtc.yaml | 61 +++++++++++++++++++ 2 files changed, 61 insertions(+), 25 deletions(-) delete mode 100644 Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.txt create mode 100644 Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.yaml diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.txt b/Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.txt deleted file mode 100644 index 3f0e2a5950eb..000000000000 --- a/Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.txt +++ /dev/null @@ -1,25 +0,0 @@ -Atmel AT91SAM9260 Real Time Timer - -Required properties: -- compatible: should be one of the following: - - "atmel,at91sam9260-rtt" - - "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt" -- reg: should encode the memory region of the RTT controller -- interrupts: rtt alarm/event interrupt -- clocks: should contain the 32 KHz slow clk that will drive the RTT block. -- atmel,rtt-rtc-time-reg: should encode the GPBR register used to store - the time base when the RTT is used as an RTC. - The first cell should point to the GPBR node and the second one - encode the offset within the GPBR block (or in other words, the - GPBR register used to store the time base). - - -Example: - -rtt@fffffd20 { - compatible = "atmel,at91sam9260-rtt"; - reg = <0xfffffd20 0x10>; - interrupts = <1 4 7>; - clocks = <&clk32k>; - atmel,rtt-rtc-time-reg = <&gpbr 0x0>; -}; diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.yaml new file mode 100644 index 000000000000..5a639c0ec2c0 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/atmel,at91sam9-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel AT91 RTT Device Tree Bindings + +allOf: + - $ref: "rtc.yaml#" + +maintainers: + - Alexandre Belloni + +properties: + compatible: + oneOf: + - items: + - const: atmel,at91sam9260-rtt + - items: + - const: microchip,sam9x60-rtt + - const: atmel,at91sam9260-rtt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + atmel,rtt-rtc-time-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + Should encode the GPBR register used to store the time base when the + RTT is used as an RTC. The first cell should point to the GPBR node + and the second one encodes the offset within the GPBR block (or in + other words, the GPBR register used to store the time base). + + start-year: true + +required: + - compatible + - reg + - interrupts + - clocks + - atmel,rtt-rtc-time-reg + +additionalProperties: false + +examples: + - | + rtc@fffffd20 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd20 0x10>; + interrupts = <1 4 7>; + clocks = <&clk32k>; + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + };