From patchwork Fri Mar 4 06:31:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tommy Huang X-Patchwork-Id: 12769063 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D07DC433F5 for ; Fri, 4 Mar 2022 13:11:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=5EBc/VZSRfH0VSotLmOya/oKU5Q47fnj+OLtWnrOdpM=; b=o2idycsBm1CPiB OAELS+S8wU6fnJa92EJ4pVLm7w5Ep35l0fADaNSpcCvv7wKXEfA0FWnUF4WdXxFFe0Ud27NRQvw9y zCnLhppCGV0ZglmJTm5LtSXbhrrkovJB4IKDDO4km5Kop3X84JgchOrXlKMP6MadQ1SNzU1o+Lsv9 tSdRQUFDOn2goiCtH5oTlkwpjbwMgQdGQnnJV06fqq4a9P8/u1+9siiVs3ARFSJZ1eF7n7S0Q47Y0 vloVBeHb1ng5amq0aB9yxITQs8ZNCzFXDpuqWVreUJUMJoYhL1pQwlz1HRqb9B49PlRfLRydsJYFg 1jlHSdNIpsOO/6LZ3/MQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQ7h8-00A4mq-Ny; Fri, 04 Mar 2022 13:10:06 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQ7h5-00A4lA-Nd for linux-arm-kernel@bombadil.infradead.org; Fri, 04 Mar 2022 13:10:03 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Type:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:CC:To:From:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=pU7VvfpdY9DVF6eqY8bc8CskjTjdtuvzjfIUZocn8Kw=; b=PAYACZQM9r+OZI8JU7r7RE1cXU +v3Vb/IrpmuFpMkgoO62+CIL1xcWQrnxJD4bt+nb4a1KNgHXtn1MZHwphBCk9SKys5Zjw6I+6fA4z /ap5CmxkDKduqXqcBqFCHx0+Pe8NVv9tXiSj6unSPT1bPc80aoW9Rse7Woo3lGHZSwIaxK/5R3jZe Xs/DHJsR/ciBNue24TRDF5oehwXUV31x9JyNc4lMh5RasVuZfmh6RSHixlZ8vw+zj6qapRtOv7b+w EeJuZ60cTS77NcAYmfHM0JGUJNPWTZaNn7clkOsXo6GvLJwP21f4CNBLxiMXn5Qg43bVk09SXOcFT EppCRD6g==; Received: from twspam01.aspeedtech.com ([211.20.114.71]) by desiato.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQ1UW-00F7IO-Kb for linux-arm-kernel@lists.infradead.org; Fri, 04 Mar 2022 06:32:42 +0000 Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 2246MIcb041906; Fri, 4 Mar 2022 14:22:18 +0800 (GMT-8) (envelope-from tommy_huang@aspeedtech.com) Received: from tommy0527-VirtualBox.aspeedtech.com (192.168.2.141) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 4 Mar 2022 14:31:44 +0800 From: Tommy Haung To: , , , , , , , , , CC: Subject: [PATCH v1 2/2] drm/aspeed: Add 1024x768 mode for AST2600 Date: Fri, 4 Mar 2022 14:31:37 +0800 Message-ID: <20220304063137.12970-3-tommy_huang@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220304063137.12970-1-tommy_huang@aspeedtech.com> References: <20220304063137.12970-1-tommy_huang@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.2.141] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 2246MIcb041906 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220304_063241_241794_39201B6B X-CRM114-Status: GOOD ( 15.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Update the aspeed_gfx_set_clk with display width. At AST2600, the display clock could be coming from HPLL clock / 16 = 75MHz. It would fit 1024x768@70Hz. Another chip will still keep 800x600. Signed-off-by: Tommy Haung --- drivers/gpu/drm/aspeed/aspeed_gfx.h | 12 ++++++---- drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c | 29 ++++++++++++++++++++---- drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 16 +++++++++++-- drivers/gpu/drm/aspeed/aspeed_gfx_out.c | 14 +++++++++++- 4 files changed, 60 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx.h b/drivers/gpu/drm/aspeed/aspeed_gfx.h index eb4c267cde5e..c7aefee0657a 100644 --- a/drivers/gpu/drm/aspeed/aspeed_gfx.h +++ b/drivers/gpu/drm/aspeed/aspeed_gfx.h @@ -109,11 +109,15 @@ int aspeed_gfx_create_output(struct drm_device *drm); #define CRT_THROD_HIGH(x) ((x) << 8) /* SCU control */ -#define SCU_G6_CLK_COURCE 0x300 +#define G6_CLK_SOURCE 0x300 +#define G6_CLK_SOURCE_MASK (BIT(8) | BIT(9) | BIT(10)) +#define G6_CLK_SOURCE_HPLL (BIT(8) | BIT(9) | BIT(10)) +#define G6_CLK_SOURCE_USB BIT(9) +#define G6_CLK_SEL3 0x308 +#define G6_CLK_DIV_MASK 0x3F000 +#define G6_CLK_DIV_16 (BIT(16)|BIT(15)|BIT(13)|BIT(12)) +#define G6_USB_40_CLK BIT(9) /* GFX FLAGS */ #define CLK_MASK BIT(0) #define CLK_G6 BIT(0) - -#define G6_CLK_MASK (BIT(8) | BIT(9) | BIT(10)) -#define G6_USB_40_CLK BIT(9) diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c index a24fab22eac4..5829be9c7c67 100644 --- a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c @@ -23,6 +23,28 @@ drm_pipe_to_aspeed_gfx(struct drm_simple_display_pipe *pipe) return container_of(pipe, struct aspeed_gfx, pipe); } +static void aspeed_gfx_set_clock_source(struct aspeed_gfx *priv, int mode_width) +{ + regmap_update_bits(priv->scu, G6_CLK_SOURCE, G6_CLK_SOURCE_MASK, 0x0); + regmap_update_bits(priv->scu, G6_CLK_SEL3, G6_CLK_DIV_MASK, 0x0); + + switch (mode_width) { + case 1024: + /* hpll div 16 = 75Mhz */ + regmap_update_bits(priv->scu, G6_CLK_SOURCE, + G6_CLK_SOURCE_MASK, G6_CLK_SOURCE_HPLL); + regmap_update_bits(priv->scu, G6_CLK_SEL3, + G6_CLK_DIV_MASK, G6_CLK_DIV_16); + break; + case 800: + default: + /* usb 40Mhz */ + regmap_update_bits(priv->scu, G6_CLK_SOURCE, + G6_CLK_SOURCE_MASK, G6_CLK_SOURCE_USB); + break; + } +} + static int aspeed_gfx_set_pixel_fmt(struct aspeed_gfx *priv, u32 *bpp) { struct drm_crtc *crtc = &priv->pipe.crtc; @@ -77,12 +99,11 @@ static void aspeed_gfx_disable_controller(struct aspeed_gfx *priv) regmap_update_bits(priv->scu, priv->dac_reg, BIT(16), 0); } -static void aspeed_gfx_set_clk(struct aspeed_gfx *priv) +static void aspeed_gfx_set_clk(struct aspeed_gfx *priv, int mode_width) { switch (priv->flags & CLK_MASK) { case CLK_G6: - regmap_update_bits(priv->scu, SCU_G6_CLK_COURCE, G6_CLK_MASK, 0x0); - regmap_update_bits(priv->scu, SCU_G6_CLK_COURCE, G6_CLK_MASK, G6_USB_40_CLK); + aspeed_gfx_set_clock_source(priv, mode_width); break; default: break; @@ -99,7 +120,7 @@ static void aspeed_gfx_crtc_mode_set_nofb(struct aspeed_gfx *priv) if (err) return; - aspeed_gfx_set_clk(priv); + aspeed_gfx_set_clk(priv, m->hdisplay); #if 0 /* TODO: we have only been able to test with the 40MHz USB clock. The diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c index af56ffdccc65..e1a814aebc2d 100644 --- a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c @@ -110,6 +110,7 @@ static const struct drm_mode_config_funcs aspeed_gfx_mode_config_funcs = { static int aspeed_gfx_setup_mode_config(struct drm_device *drm) { + struct aspeed_gfx *priv = to_aspeed_gfx(drm); int ret; ret = drmm_mode_config_init(drm); @@ -118,8 +119,18 @@ static int aspeed_gfx_setup_mode_config(struct drm_device *drm) drm->mode_config.min_width = 0; drm->mode_config.min_height = 0; - drm->mode_config.max_width = 800; - drm->mode_config.max_height = 600; + + switch (priv->flags & CLK_MASK) { + case CLK_G6: + drm->mode_config.max_width = 1024; + drm->mode_config.max_height = 768; + break; + default: + drm->mode_config.max_width = 800; + drm->mode_config.max_height = 600; + break; + } + drm->mode_config.funcs = &aspeed_gfx_mode_config_funcs; return ret; @@ -167,6 +178,7 @@ static int aspeed_gfx_load(struct drm_device *drm) priv->vga_scratch_reg = config->vga_scratch_reg; priv->throd_val = config->throd_val; priv->scan_line_max = config->scan_line_max; + priv->flags = config->gfx_flags; priv->scu = syscon_regmap_lookup_by_phandle(np, "syscon"); if (IS_ERR(priv->scu)) { diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_out.c b/drivers/gpu/drm/aspeed/aspeed_gfx_out.c index 6759cb88415a..5d5e04f15c59 100644 --- a/drivers/gpu/drm/aspeed/aspeed_gfx_out.c +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_out.c @@ -10,7 +10,19 @@ static int aspeed_gfx_get_modes(struct drm_connector *connector) { - return drm_add_modes_noedid(connector, 800, 600); + struct aspeed_gfx *priv = container_of(connector, struct aspeed_gfx, connector); + int mode_count = 0; + + switch (priv->flags & CLK_MASK) { + case CLK_G6: + mode_count = drm_add_modes_noedid(connector, 1024, 768); + break; + default: + mode_count = drm_add_modes_noedid(connector, 800, 600); + break; + } + + return mode_count; } static const struct