From patchwork Fri Mar 4 13:35:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12769130 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D3C3BC433EF for ; Fri, 4 Mar 2022 13:37:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=WqbRuuqV2glvrac1EDcRfwC9bpaCdaiEs3vmxH+YRwM=; b=T7WcxwbGxsfhIb mvE1/38ZDhsSkeMa7EASasLafMaYo/SWiEp02mhDrTBuwk3QiFdRq4C5hEmaLORF6lFDxQrhLTZmt Wj1MyFg2Z8dWIAUy4x2D/NvhzcnMaqQ6Q9Eeoi71rbICHeOR5MVORNVOgz25TCakN573WpPCdT/Sy OgGDyV3+FC4qE4crqDi/P1B8aWT1yh94QttY/E96b3b5+lD4qYlJ0AbPawipLGBGJfpYSUYookesb 05LuKLHTVlMvyEa6zd5jSdF+KYoxC3eJ8x7ouwM6DDxYXSZHX3Dg6DYaGjxdiZMuAK/QazS46jTw6 cUxBAYIcIfpFOWWbiFIw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQ86V-00AGgs-Jq; Fri, 04 Mar 2022 13:36:20 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQ85D-00AG7p-Go for linux-arm-kernel@lists.infradead.org; Fri, 04 Mar 2022 13:35:01 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646400899; x=1677936899; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Jti6Lf93/pkshsUoxGsmUk/NZEDKA40Cet1PtYYdvz4=; b=azHX1+yh498A+4U3FYqDLGhFP9P/LaZJ8jma93Yc1vhZMfOBZ1nsA6Db EC9hT6on9Zg+nbC1SL6LFIkfBYhpuT6j4REvZi6saVWrInr0OeYpCHhKP dY+U8DM24l9BYodrFp0+0UMlQHdxNSCWqMhJ5oUye0XlWNW3s5FgImfZ3 wrIAiHt+L+JZUUkrN+CanwLltsMQqQs6+ojwJFp/3WvHLEbAjzoNr4g/A j8D9E5cn4T37LRYMKCLe3lAPQRbAEgNdz+Kk9xLeHkHNI6YVQs23awkw8 PdYUf4UVMiG5NI6e+cSZLydlYMhg7NmxlCEB5c7EVi2yyZ5SReWFYBNlz A==; X-IronPort-AV: E=Sophos;i="5.90,155,1643698800"; d="scan'208";a="148098685" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 04 Mar 2022 06:34:58 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 4 Mar 2022 06:34:58 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 4 Mar 2022 06:34:56 -0700 From: Claudiu Beznea To: , CC: , , Claudiu Beznea Subject: [PATCH v3 3/6] clocksource/drivers/timer-microchip-pit64b: use 5MHz for clockevent Date: Fri, 4 Mar 2022 15:35:58 +0200 Message-ID: <20220304133601.2404086-4-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220304133601.2404086-1-claudiu.beznea@microchip.com> References: <20220304133601.2404086-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220304_053459_673710_ACD84D43 X-CRM114-Status: GOOD ( 11.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Use 5MHz clock for clockevent timers. This increases timer's resolution. Signed-off-by: Claudiu Beznea --- drivers/clocksource/timer-microchip-pit64b.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/timer-microchip-pit64b.c b/drivers/clocksource/timer-microchip-pit64b.c index 790d2c9b42a7..abce83d2f00b 100644 --- a/drivers/clocksource/timer-microchip-pit64b.c +++ b/drivers/clocksource/timer-microchip-pit64b.c @@ -42,8 +42,7 @@ #define MCHP_PIT64B_LSBMASK GENMASK_ULL(31, 0) #define MCHP_PIT64B_PRES_TO_MODE(p) (MCHP_PIT64B_MR_PRES & ((p) << 8)) #define MCHP_PIT64B_MODE_TO_PRES(m) ((MCHP_PIT64B_MR_PRES & (m)) >> 8) -#define MCHP_PIT64B_DEF_CS_FREQ 5000000UL /* 5 MHz */ -#define MCHP_PIT64B_DEF_CE_FREQ 32768 /* 32 KHz */ +#define MCHP_PIT64B_DEF_FREQ 5000000UL /* 5 MHz */ #define MCHP_PIT64B_NAME "pit64b" @@ -418,7 +417,6 @@ static int __init mchp_pit64b_init_clkevt(struct mchp_pit64b_timer *timer, static int __init mchp_pit64b_dt_init_timer(struct device_node *node, bool clkevt) { - u32 freq = clkevt ? MCHP_PIT64B_DEF_CE_FREQ : MCHP_PIT64B_DEF_CS_FREQ; struct mchp_pit64b_timer timer; unsigned long clk_rate; u32 irq = 0; @@ -446,7 +444,7 @@ static int __init mchp_pit64b_dt_init_timer(struct device_node *node, } /* Initialize mode (prescaler + SGCK bit). To be used at runtime. */ - ret = mchp_pit64b_init_mode(&timer, freq); + ret = mchp_pit64b_init_mode(&timer, MCHP_PIT64B_DEF_FREQ); if (ret) goto irq_unmap;