From patchwork Fri Mar 4 13:35:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12769131 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0E127C433EF for ; Fri, 4 Mar 2022 13:38:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pDwV6SuxwEElEVTxOXb2BwtZXghkaWTQDxqfOCkY59E=; b=JYJIWg4JAWqtJk zEwoABzCvDrtc89P8AR/YAYsQgEPd5m5EujJpxJvzIkTPNYTgMRyzbGtxdahe8katSqIteo0ijC5w jnYfSQzNcQVxM0dhaPa/IJKAM6aDyiYqX5f7lwaZ3oYtvKVzgD4Rp0N6YcFZJ23MfFZViRmDPLhks I7/T7VUn+nipHuwyH/a5cSaFMqB/2hd6KyLUwXods5c6lyb6Z+hgA7xcqj8xqcVToPsHB/Ko4v1ot KK4iFzsZtBvRC77m8HfST8B8e70YpMg4P5RAtCI2CvptKegN8WCzZsOfIVrnWr9qZO8r/72fGSXCp EyVZGLhMT6fnpc4BOS8Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQ87E-00AH24-2r; Fri, 04 Mar 2022 13:37:05 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQ85F-00AGAi-Vm for linux-arm-kernel@lists.infradead.org; Fri, 04 Mar 2022 13:35:03 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646400901; x=1677936901; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CGECGO3DLDF9kAjkJpmPmmKockfvvVD5RT0cNRq2/PE=; b=Y0USkb2ZBl0vrjI2e8UInGT1IBXaeVI9ALniq3ArF8YcVA8LupJ/UlX9 r5LHgokNy43cb1HnVqHfWIWVPUPAAANl53mh1RQilxAw+iXaJwfIFEdOG 6BQXTm9yD70p51hv4dRId3HUwQAJzRHIFGpVeoJN7omuOsU65v/ukfQ+M fLKv4U9ySuG3l0qm5OKHTrOVqlm13WHhaDunwayWoxFalpw9k9Me6M9D3 46KGJ8zCAb5zNNTyysYczpxuwo8+6pOITBZqqcCSvq13wGxdLWfhVaBw/ EVlw1yd/h/k8jNmEoPk29SqdT84g8HjwKC2CKocY9gc5o+XFzL/iT+2UW w==; X-IronPort-AV: E=Sophos;i="5.90,155,1643698800"; d="scan'208";a="87833826" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 04 Mar 2022 06:35:00 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 4 Mar 2022 06:35:00 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 4 Mar 2022 06:34:58 -0700 From: Claudiu Beznea To: , CC: , , Claudiu Beznea Subject: [PATCH v3 4/6] clocksource/drivers/timer-microchip-pit64b: remove suspend/resume ops for ce Date: Fri, 4 Mar 2022 15:35:59 +0200 Message-ID: <20220304133601.2404086-5-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220304133601.2404086-1-claudiu.beznea@microchip.com> References: <20220304133601.2404086-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220304_053502_202477_F1B3C4C7 X-CRM114-Status: GOOD ( 12.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Remove suspend and resume ops for clockevent and add set_state_oneshot() instead. Along with this mchp_pit64b_{suspend, resume}() were called on proper function to disable/enable clocks. This will allow disabling clocks for clockevent in case it is not selected as active clockevent. Signed-off-by: Claudiu Beznea --- drivers/clocksource/timer-microchip-pit64b.c | 30 +++++++++++--------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/clocksource/timer-microchip-pit64b.c b/drivers/clocksource/timer-microchip-pit64b.c index abce83d2f00b..b51259395ac3 100644 --- a/drivers/clocksource/timer-microchip-pit64b.c +++ b/drivers/clocksource/timer-microchip-pit64b.c @@ -173,7 +173,8 @@ static int mchp_pit64b_clkevt_shutdown(struct clock_event_device *cedev) { struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); - writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR); + if (!clockevent_state_detached(cedev)) + mchp_pit64b_suspend(timer); return 0; } @@ -182,35 +183,37 @@ static int mchp_pit64b_clkevt_set_periodic(struct clock_event_device *cedev) { struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); + if (clockevent_state_shutdown(cedev)) + mchp_pit64b_resume(timer); + mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_CONT, MCHP_PIT64B_IER_PERIOD); return 0; } -static int mchp_pit64b_clkevt_set_next_event(unsigned long evt, - struct clock_event_device *cedev) +static int mchp_pit64b_clkevt_set_oneshot(struct clock_event_device *cedev) { struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); - mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT, + if (clockevent_state_shutdown(cedev)) + mchp_pit64b_resume(timer); + + mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_ONE_SHOT, MCHP_PIT64B_IER_PERIOD); return 0; } -static void mchp_pit64b_clkevt_suspend(struct clock_event_device *cedev) +static int mchp_pit64b_clkevt_set_next_event(unsigned long evt, + struct clock_event_device *cedev) { struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); - mchp_pit64b_suspend(timer); -} - -static void mchp_pit64b_clkevt_resume(struct clock_event_device *cedev) -{ - struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); + mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT, + MCHP_PIT64B_IER_PERIOD); - mchp_pit64b_resume(timer); + return 0; } static irqreturn_t mchp_pit64b_interrupt(int irq, void *dev_id) @@ -395,9 +398,8 @@ static int __init mchp_pit64b_init_clkevt(struct mchp_pit64b_timer *timer, ce->clkevt.rating = 150; ce->clkevt.set_state_shutdown = mchp_pit64b_clkevt_shutdown; ce->clkevt.set_state_periodic = mchp_pit64b_clkevt_set_periodic; + ce->clkevt.set_state_oneshot = mchp_pit64b_clkevt_set_oneshot; ce->clkevt.set_next_event = mchp_pit64b_clkevt_set_next_event; - ce->clkevt.suspend = mchp_pit64b_clkevt_suspend; - ce->clkevt.resume = mchp_pit64b_clkevt_resume; ce->clkevt.cpumask = cpumask_of(0); ce->clkevt.irq = irq;