From patchwork Fri Mar 4 14:27:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12769213 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A5A94C433F5 for ; Fri, 4 Mar 2022 14:30:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=gfNThA4ggIiY4vhm1NWhSUM+DZhXf4DR02upWo4G8cc=; b=n1a4nJLseTkrb9 m0CWBpRadff7x4e2Og+pOJGT2T952v9is/jcS/GD75wA9Oz2UL/vFQFRMuB21O2ntsgK+PbMyDMmm 4j1MQMw3lr1rjWkaLn0JebgfvsO0NeGlpHG3RQGykUmm+Oiq+2P1myovSD/25yu32gMJ3n7tPKm3X ot/cDKgT0USdEa4Exu4JI9i1IiAzLvSjQ4LfbM94eHU/2/klYAQ9jEuiq01zBbpb1VEnNoyk6gOTL fBNHUsI5EuzJnIG5b3XBi4grh7yPPJ1sVjOXHhHiqXz3IULdOyryFuxAeb92sh5apALBXk6OMgBaM NjKv/oY9C+o8Khhm+6Ig==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQ8wE-00ATxy-9y; Fri, 04 Mar 2022 14:29:46 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQ8vj-00ATiL-OF for linux-arm-kernel@lists.infradead.org; Fri, 04 Mar 2022 14:29:17 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646404155; x=1677940155; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fwVOUiLoniEcyoRU/rHNkAjvOoKHUwW8030ZeEGzBSI=; b=Yc3IG7FA+TypQmC1g2SOexL7vpeGg6jtQ4luWZrEZl8UaU169EAvzI0J w5bJg7XgH0rtqjpqi3KTg50sVbHJijcq3Wcr4Plnx1OS+/oVTjkLhaxCJ 5Nlu785CcFBdxm44JTIsOAjb5iy5bojHPQxUfDLdidpT+bFJxSZ3H0G48 ZKTEKVDSHOaCNUfOSALlwNapOzZ81DBXZuLan7T3aCEEUcqn6I1znGf5I WzF1bFXGNU0zQeCZ0JLOXsb15kVG65rbVyfg5drToX9FhHhSJ7URC63yR zHZXRx/EZUUixFecuCr5Ioq6SJI2hvGS5ZInyBIku8Lt0csCVT45GhRHf g==; X-IronPort-AV: E=Sophos;i="5.90,155,1643698800"; d="scan'208";a="155733482" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 04 Mar 2022 07:29:15 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 4 Mar 2022 07:29:14 -0700 Received: from ROB-ULT-M68701.amer.actel.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 4 Mar 2022 07:29:11 -0700 From: Sergiu Moga To: , , , , , CC: , , , , Sergiu Moga Subject: [PATCH v3 3/5] dt-bindings: rtc: convert at91sam9 bindings to json-schema Date: Fri, 4 Mar 2022 16:27:44 +0200 Message-ID: <20220304142746.121947-4-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220304142746.121947-1-sergiu.moga@microchip.com> References: <20220304142746.121947-1-sergiu.moga@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220304_062915_860194_C14293E6 X-CRM114-Status: GOOD ( 17.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert RTC binding for Atmel/Microchip SoCs to Device Tree Schema format. Signed-off-by: Sergiu Moga --- .../bindings/rtc/atmel,at91sam9-rtc.txt | 25 -------- .../bindings/rtc/atmel,at91sam9-rtc.yaml | 63 +++++++++++++++++++ 2 files changed, 63 insertions(+), 25 deletions(-) delete mode 100644 Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.txt create mode 100644 Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.yaml diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.txt b/Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.txt deleted file mode 100644 index 3f0e2a5950eb..000000000000 --- a/Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.txt +++ /dev/null @@ -1,25 +0,0 @@ -Atmel AT91SAM9260 Real Time Timer - -Required properties: -- compatible: should be one of the following: - - "atmel,at91sam9260-rtt" - - "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt" -- reg: should encode the memory region of the RTT controller -- interrupts: rtt alarm/event interrupt -- clocks: should contain the 32 KHz slow clk that will drive the RTT block. -- atmel,rtt-rtc-time-reg: should encode the GPBR register used to store - the time base when the RTT is used as an RTC. - The first cell should point to the GPBR node and the second one - encode the offset within the GPBR block (or in other words, the - GPBR register used to store the time base). - - -Example: - -rtt@fffffd20 { - compatible = "atmel,at91sam9260-rtt"; - reg = <0xfffffd20 0x10>; - interrupts = <1 4 7>; - clocks = <&clk32k>; - atmel,rtt-rtc-time-reg = <&gpbr 0x0>; -}; diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.yaml new file mode 100644 index 000000000000..af25cc275356 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/atmel,at91sam9-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel AT91 RTT Device Tree Bindings + +allOf: + - $ref: "rtc.yaml#" + +maintainers: + - Alexandre Belloni + +properties: + compatible: + oneOf: + - items: + - const: atmel,at91sam9260-rtt + - items: + - const: microchip,sam9x60-rtt + - const: atmel,at91sam9260-rtt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + atmel,rtt-rtc-time-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to the GPBR node. + - description: Offset within the GPBR block. + description: + Should encode the GPBR register used to store the time base when the + RTT is used as an RTC. The first cell should point to the GPBR node + and the second one encodes the offset within the GPBR block (or in + other words, the GPBR register used to store the time base). + +required: + - compatible + - reg + - interrupts + - clocks + - atmel,rtt-rtc-time-reg + +unevaluatedProperties: false + +examples: + - | + rtc@fffffd20 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd20 0x10>; + interrupts = <1 4 7>; + clocks = <&clk32k>; + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + };