From patchwork Tue Mar 8 20:49:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12774372 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2D0BEC433F5 for ; Tue, 8 Mar 2022 20:52:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=rpoKJI7cB0xvNlgnkZIcQRWJVwmI9KIJHXFk1+AwkRY=; b=OhJLySQIeGTo8s FJCX9TkIfukgO5RqKVVBsbbNzgOHBHMcM3c3zTq7smwpR6kpvbipGKCXa8IqyZhidLDVKFzkt0NPR qUIyRQzBGSpIyS2MoS2xHfoITz9qL5j6EA9DNBWtMb8srvCjKh+H0H5rTApC3rlAbMOMejMR8A9wc 2bVFi57czfItTOhvrjyHaRN5wvbOy/rW/6JlttkovmOaqRO7oXQ4sidp9L++pLZYnyQvU/li/6HeT 34Pix6qa/H5Wb8Gw/J+cqvUf+RA8DkMc3ecbBTH1tftQKxX6pcm6/XCXrOgSD2Q/MwtslRxhwPcMT PYAH1n6hH1r7YCstZklg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRgnf-006CIv-HI; Tue, 08 Mar 2022 20:51:19 +0000 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRgmY-006Bp0-4v for linux-arm-kernel@lists.infradead.org; Tue, 08 Mar 2022 20:50:13 +0000 Received: by mail-wm1-x32b.google.com with SMTP id c192so189568wma.4 for ; Tue, 08 Mar 2022 12:50:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3UYsDt0yevSXQ6U7sc5n3heP9iPsGQbfHAheP1SRQC0=; b=auI060en4E3ZPAf8X25iTbQJE8jh5ycpsEJ5Q8k7glIQpTu8k3NDu6+Qv7ksLDRFxi 7tOUzoOCvNJDXLw42STAF1r+vkHThpNcFIEe7bOQ9/f89XwPXxexWwaew2CGGsRHF3eq qgjwsx72XgAmSrIs9mDQImHczWZSxZPsAcUfmAVM+ZosIfrxVQ4B+Rx/d+iEv5NBN+e4 xqnHbdf/ICU1VMl1Dp3NKNQUUrRqBGlQPxYsEKAtGNi0E5DJdZTBEwt2TG4p4Qx5NsaG RLTNPpCPB0ijF0HN4rX3O1RMFjP2iWHfmqjfnIT3LbAKzSpP3hcZZYLZOzH/bxtFE1wg a6JQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3UYsDt0yevSXQ6U7sc5n3heP9iPsGQbfHAheP1SRQC0=; b=bWy7PJPM6f4QIVGVW9cf+vPeP8spfSebWqit3rGUxOn278klxK25r6mqFakjbJ7xnh vDKhoGtq9p62d3v/T0rwBY8WVnnLxzL5j+e9e8lExvd7A1tk1j4BeBJyq65LTpPRIGl8 RPEymlmIZkcz+7+kCBmuNfeGhFI75krHwg6zVhkZySYBjL7THPAYGy1jG8OCRVnFDfJi Irmfw7XXc4+AfymkhejvoyPf6rtFviNaJt3nl3KSd0JivAFADNrli8gULANjGL4MOTD0 AHTFf6nBefLrtkmMYZPiA7mw1rFherqTP78IYpAdDkfn9EVtJWXdQL7AnxFpRVsyrxGv 15uA== X-Gm-Message-State: AOAM531joXqWeh64LBYnDAYtD6ot+prPaT1T3jfcB0Ac/Z9WibZ4A68/ V1PnLsV+EaiTEiAhRMKYpHU2LQ== X-Google-Smtp-Source: ABdhPJy4EpWC1e2s5DMrlTr7d8Uw23sh3sZffOhSADmfSzqqHMRWiAp9osQRbbcU/vCgll2yOS2sNg== X-Received: by 2002:a05:600c:b4d:b0:382:ab98:f470 with SMTP id k13-20020a05600c0b4d00b00382ab98f470mr890047wmr.8.1646772608956; Tue, 08 Mar 2022 12:50:08 -0800 (PST) Received: from linaro.org ([2a00:23c5:6809:2201:546d:7d59:1703:bf96]) by smtp.gmail.com with ESMTPSA id p26-20020a1c741a000000b00389ab9a53c8sm3245758wmc.36.2022.03.08.12.50.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Mar 2022 12:50:08 -0800 (PST) From: Mike Leach To: suzuki.poulose@arm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, Mike Leach Subject: [PATCH 05/10] coresight: etm3x: Use trace ID API to allocate IDs Date: Tue, 8 Mar 2022 20:49:55 +0000 Message-Id: <20220308205000.27646-6-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220308205000.27646-1-mike.leach@linaro.org> References: <20220308205000.27646-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220308_125010_243560_B458820C X-CRM114-Status: GOOD ( 21.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Use the TraceID API to allocate ETM trace IDs dynamically. As with the etm4x we allocate on enable / disable for perf, allocate on enable / reset for sysfs. Additionally we allocate on sysfs file read as both perf and sysfs can read the ID before enabling the hardware. Remove sysfs option to write trace ID - which is inconsistent with both the dynamic allocation method and the fixed allocation method previously used. Signed-off-by: Mike Leach --- drivers/hwtracing/coresight/coresight-etm.h | 2 + .../coresight/coresight-etm3x-core.c | 72 ++++++++++++++++--- .../coresight/coresight-etm3x-sysfs.c | 28 +++----- 3 files changed, 71 insertions(+), 31 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h index f3ab96eaf44e..3667428d38b6 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -287,4 +287,6 @@ int etm_get_trace_id(struct etm_drvdata *drvdata); void etm_set_default(struct etm_config *config); void etm_config_trace_mode(struct etm_config *config); struct etm_config *get_etm_config(struct etm_drvdata *drvdata); +int etm_read_alloc_trace_id(struct etm_drvdata *drvdata); +void etm_release_trace_id(struct etm_drvdata *drvdata); #endif diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index 7d413ba8b823..98213503bd09 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -32,6 +32,7 @@ #include "coresight-etm.h" #include "coresight-etm-perf.h" +#include "coresight-trace-id.h" /* * Not really modular but using module_param is the easiest way to @@ -490,18 +491,57 @@ static int etm_trace_id(struct coresight_device *csdev) return etm_get_trace_id(drvdata); } +int etm_read_alloc_trace_id(struct etm_drvdata *drvdata) +{ + int trace_id; + + /* + * This will allocate a trace ID to the cpu, + * or return the one currently allocated. + */ + trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu, + coresight_get_trace_id_map()); + if (trace_id > 0) { + spin_lock(&drvdata->spinlock); + drvdata->traceid = (u8)trace_id; + spin_unlock(&drvdata->spinlock); + } else { + pr_err("Failed to allocate trace ID for %s on CPU%d\n", + dev_name(&drvdata->csdev->dev), drvdata->cpu); + } + return trace_id; +} + +void etm_release_trace_id(struct etm_drvdata *drvdata) +{ + coresight_trace_id_put_cpu_id(drvdata->cpu, + coresight_get_trace_id_map()); + spin_lock(&drvdata->spinlock); + drvdata->traceid = 0; + spin_unlock(&drvdata->spinlock); +} + static int etm_enable_perf(struct coresight_device *csdev, struct perf_event *event) { struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + int ret; if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) return -EINVAL; + ret = etm_read_alloc_trace_id(drvdata); + if (ret < 0) + return ret; + /* Configure the tracer based on the session's specifics */ etm_parse_event_config(drvdata, event); /* And enable it */ - return etm_enable_hw(drvdata); + ret = etm_enable_hw(drvdata); + + if (ret) + etm_release_trace_id(drvdata); + return ret; } static int etm_enable_sysfs(struct coresight_device *csdev) @@ -510,6 +550,10 @@ static int etm_enable_sysfs(struct coresight_device *csdev) struct etm_enable_arg arg = { }; int ret; + ret = etm_read_alloc_trace_id(drvdata); + if (ret < 0) + return ret; + spin_lock(&drvdata->spinlock); /* @@ -532,6 +576,8 @@ static int etm_enable_sysfs(struct coresight_device *csdev) if (!ret) dev_dbg(&csdev->dev, "ETM tracing enabled\n"); + else + etm_release_trace_id(drvdata); return ret; } @@ -611,6 +657,8 @@ static void etm_disable_perf(struct coresight_device *csdev) coresight_disclaim_device_unlocked(csdev); CS_LOCK(drvdata->base); + + etm_release_trace_id(drvdata); } static void etm_disable_sysfs(struct coresight_device *csdev) @@ -781,11 +829,6 @@ static void etm_init_arch_data(void *info) CS_LOCK(drvdata->base); } -static void etm_init_trace_id(struct etm_drvdata *drvdata) -{ - drvdata->traceid = coresight_get_trace_id(drvdata->cpu); -} - static int __init etm_hp_setup(void) { int ret; @@ -871,7 +914,6 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) if (etm_arch_supported(drvdata->arch) == false) return -EINVAL; - etm_init_trace_id(drvdata); etm_set_default(&drvdata->config); pdata = coresight_get_platform_data(dev); @@ -891,10 +933,12 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR(drvdata->csdev); ret = etm_perf_symlink(drvdata->csdev, true); - if (ret) { - coresight_unregister(drvdata->csdev); - return ret; - } + if (ret) + goto cs_unregister; + + ret = etm_read_alloc_trace_id(drvdata); + if (ret < 0) + goto cs_unregister; etmdrvdata[drvdata->cpu] = drvdata; @@ -907,6 +951,10 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) } return 0; + +cs_unregister: + coresight_unregister(drvdata->csdev); + return ret; } static void clear_etmdrvdata(void *info) @@ -922,6 +970,8 @@ static void etm_remove(struct amba_device *adev) etm_perf_symlink(drvdata->csdev, false); + etm_release_trace_id(drvdata); + /* * Taking hotplug lock here to avoid racing between etm_remove and * CPU hotplug call backs. diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c index e8c7649f123e..3ee70b174240 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c @@ -86,6 +86,8 @@ static ssize_t reset_store(struct device *dev, etm_set_default(config); spin_unlock(&drvdata->spinlock); + /* release trace id outside the spinlock as this fn uses it */ + etm_release_trace_id(drvdata); } return size; @@ -1189,30 +1191,16 @@ static DEVICE_ATTR_RO(cpu); static ssize_t traceid_show(struct device *dev, struct device_attribute *attr, char *buf) { - unsigned long val; - struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); - - val = etm_get_trace_id(drvdata); - - return sprintf(buf, "%#lx\n", val); -} - -static ssize_t traceid_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t size) -{ - int ret; - unsigned long val; + int trace_id; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); - ret = kstrtoul(buf, 16, &val); - if (ret) - return ret; + trace_id = etm_read_alloc_trace_id(drvdata); + if (trace_id < 0) + return trace_id; - drvdata->traceid = val & ETM_TRACEID_MASK; - return size; + return sprintf(buf, "%#x\n", trace_id); } -static DEVICE_ATTR_RW(traceid); +static DEVICE_ATTR_RO(traceid); static struct attribute *coresight_etm_attrs[] = { &dev_attr_nr_addr_cmp.attr,