From patchwork Wed Mar 9 12:07:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12775006 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C8CCEC433EF for ; Wed, 9 Mar 2022 12:10:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9HCUPSA5WgjzBgQs3ewVgXRzm6rIE+sQNgdApIYLTqI=; b=EYXaroBID1edaQ Xno6ivvnJvmNL0+J1Z693wRB0im+2d+lBIQX9yCMJVIUQGy2lx4RM/JHPRCGezCF8vu6ntyGYgw53 lAPqZkC5hBipLgjN+jy+P1QuzntLfYr12VPob1oqxQnf6TmsYgllPWw7ptA12Q8h/RtdY6n98LfhE 6OOyGWfOcLOZA9bJeZw0x51aDAJaX1IeE4o7QonL0iiYxAv5VAtqGzSJj6p0hUwm30KdWFzBRA0Eu MhfljitXS8vE70aZ9CFRMgVcEeHCTKGVAYoo7m4e+43rFBnpmBVpIRVOYiyUlWEIXJDrFCkXXRWr2 7la2qERQPGShUzX6LB0g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRv83-008UeB-7T; Wed, 09 Mar 2022 12:09:19 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRv6l-008U44-DS for linux-arm-kernel@lists.infradead.org; Wed, 09 Mar 2022 12:08:02 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646827679; x=1678363679; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9Byu8P78w96N4rhS6oryyUAAOHS75SicuioSZJ5/sOU=; b=uUIM9QTowm5BnojGXwoVhNcQiR236dqg/8BXJpuri7bQOiPDhyibQNui sFX2CsTHSUeTM9Iqbq48QIelog3Nvp1FHfDdQ+u6SP778ZCyjQpDhUzJb ArEF9zgQVC86XpWTikHDvn0BjkYaTiGE93u8VYItHUGgZWDy15paeLLo+ QNXXW6suMiVEV99+zQ6ODURhi5xNJnvnrVhP6hHO/ZLQF0nqJy7/PJsqG spUJotVXGjLIq72iW/ciYTloI3Xgefm8s1J+KUoIQtmrlH4CySI4B7+LU RfzGC4GH7HlXkxlSpAcn2ynERJFF5X4CobnhZBBXhgdLWqKf9bu2I7u6O A==; X-IronPort-AV: E=Sophos;i="5.90,167,1643698800"; d="scan'208";a="156252247" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Mar 2022 05:07:43 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 9 Mar 2022 05:07:42 -0700 Received: from ROB-ULT-M68701.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Wed, 9 Mar 2022 05:07:39 -0700 From: Sergiu Moga To: , , , , CC: , , , , Sergiu Moga Subject: [PATCH 2/3] dt-bindings: i2c: convert i2c-at91 to json-schema Date: Wed, 9 Mar 2022 14:07:13 +0200 Message-ID: <20220309120714.51393-3-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220309120714.51393-1-sergiu.moga@microchip.com> References: <20220309120714.51393-1-sergiu.moga@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220309_040759_602147_0E2F86EB X-CRM114-Status: GOOD ( 16.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert I2C binding for Atmel/Microchip SoCs to Device Tree Schema format. Signed-off-by: Sergiu Moga --- .../bindings/i2c/atmel,at91sam-i2c.yaml | 144 ++++++++++++++++++ .../devicetree/bindings/i2c/i2c-at91.txt | 82 ---------- 2 files changed, 144 insertions(+), 82 deletions(-) create mode 100644 Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-at91.txt diff --git a/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml b/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml new file mode 100644 index 000000000000..d4aadbbd1a11 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/atmel,at91sam-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: I2C for Atmel/Microchip platforms + +maintainers: + - Alexandre Belloni + +allOf: + - $ref: "i2c-controller.yaml" + - if: + properties: + compatible: + contains: + enum: + - atmel,sama5d4-i2c + - atmel,sama5d2-i2c + - microchip,sam9x60-i2c + then: + properties: + i2c-sda-hold-time-ns: + description: + TWD hold time + maxItems: 1 + +properties: + compatible: + enum: + - atmel,at91rm9200-i2c + - atmel,at91sam9261-i2c + - atmel,at91sam9260-i2c + - atmel,at91sam9g20-i2c + - atmel,at91sam9g10-i2c + - atmel,at91sam9x5-i2c + - atmel,sama5d4-i2c + - atmel,sama5d2-i2c + - microchip,sam9x60-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + clocks: + maxItems: 1 + + clock-frequency: + default: 100000 + + dmas: + items: + - description: TX DMA Channel Specifier + - description: RX DMA Channel Specifier + + dma-names: + items: + - const: tx + - const: rx + + atmel,fifo-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Maximum number of data the RX and TX FIFOs can store for + FIFO capable I2C controllers. + + scl-gpios: true + + sda-gpios: true + + pinctrl: + description: | + Add extra pinctrl to configure i2c pins to gpio function for i2c + bus recovery, call it "gpio" state + +required: + - compatible + - reg + - interrupts + - "#address-cells" + - "#size-cells" + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + i2c0: i2c@fff84000 { + compatible = "atmel,at91sam9g20-i2c"; + reg = <0xfff84000 0x100>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi0_clk>; + clock-frequency = <400000>; + + eeprom@50 { + compatible = "atmel,24c512"; + reg = <0x50>; + pagesize = <128>; + }; + }; + + i2c1: i2c@f8034600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0xf8034600 0x100>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) + AT91_XDMAC_DT_PERID(11)>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) + AT91_XDMAC_DT_PERID(12)>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&flx0>; + atmel,fifo-size = <16>; + i2c-sda-hold-time-ns = <336>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + eeprom@1a { + compatible = "wm8731"; + reg = <0x1a>; + }; + }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-at91.txt b/Documentation/devicetree/bindings/i2c/i2c-at91.txt deleted file mode 100644 index 2015f50aed0f..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-at91.txt +++ /dev/null @@ -1,82 +0,0 @@ -I2C for Atmel platforms - -Required properties : -- compatible : Must be one of: - "atmel,at91rm9200-i2c", - "atmel,at91sam9261-i2c", - "atmel,at91sam9260-i2c", - "atmel,at91sam9g20-i2c", - "atmel,at91sam9g10-i2c", - "atmel,at91sam9x5-i2c", - "atmel,sama5d4-i2c", - "atmel,sama5d2-i2c", - "microchip,sam9x60-i2c". -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: interrupt number to the cpu. -- #address-cells = <1>; -- #size-cells = <0>; -- clocks: phandles to input clocks. - -Optional properties: -- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000 -- dmas: A list of two dma specifiers, one for each entry in dma-names. -- dma-names: should contain "tx" and "rx". -- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO - capable I2C controllers. -- i2c-sda-hold-time-ns: TWD hold time, only available for: - "atmel,sama5d4-i2c", - "atmel,sama5d2-i2c", - "microchip,sam9x60-i2c". -- scl-gpios: specify the gpio related to SCL pin -- sda-gpios: specify the gpio related to SDA pin -- pinctrl: add extra pinctrl to configure i2c pins to gpio function for i2c - bus recovery, call it "gpio" state -- Child nodes conforming to i2c bus binding - - -Examples : - -i2c0: i2c@fff84000 { - compatible = "atmel,at91sam9g20-i2c"; - reg = <0xfff84000 0x100>; - interrupts = <12 4 6>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&twi0_clk>; - clock-frequency = <400000>; - - 24c512@50 { - compatible = "atmel,24c512"; - reg = <0x50>; - pagesize = <128>; - } -} - -i2c0: i2c@f8034600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0xf8034600 0x100>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) - AT91_XDMAC_DT_PERID(11)>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) - AT91_XDMAC_DT_PERID(12)>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&flx0>; - atmel,fifo-size = <16>; - i2c-sda-hold-time-ns = <336>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c0>; - pinctrl-1 = <&pinctrl_i2c0_gpio>; - sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - - wm8731: wm8731@1a { - compatible = "wm8731"; - reg = <0x1a>; - }; -};