From patchwork Fri Mar 11 09:45:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Whitchurch X-Patchwork-Id: 12777722 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A116BC433F5 for ; Fri, 11 Mar 2022 09:47:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=zeV48IFkizFmS1fA0DrnG/PcdpDA07Hd0DGNob+HrS0=; b=r3qEX+xnEv6OCy p1IbiyjnCYB439WQmil7xbsnIULiX6AvcYC48q/KOJVD9xroNPcq6TC1XB6MqWLjQhG1bYAXoIvYZ Sa0yfN4LBjvX4eJP2i6pgnUUh8ul/EQ6J/fRMzBWJ5jwPUfNcG4P4Ormw2mPk8xpqefxx0vr697CO RRxloUfc5IVbkGs+OYFpBAe7bFrLY5t3+yJeQipUp/FkWU0tTLkOB3zxYH2XBBzw7Zwn6SQZKX05i O9s5DcLx9hMr6nmvYVFC7ACpSmvzcJNyv1DQ3Vd9giMZMGfCOrPyhHfmJ7F+M6MkcF3H81HGPa6A5 55YTpm5fnKaPS7pOluIQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nSbqf-00Frmr-AA; Fri, 11 Mar 2022 09:46:13 +0000 Received: from smtp2.axis.com ([195.60.68.18]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nSbpv-00FrWV-Nv for linux-arm-kernel@lists.infradead.org; Fri, 11 Mar 2022 09:45:29 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; q=dns/txt; s=axis-central1; t=1646991928; x=1678527928; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QOMLzEesVg6HYaOAZ4KCgGOM/7fxz+rqf2h1kQQi9LY=; b=Qm34IyCGdSHNXhwjgY9dZF30CWPtG+gMcUbCqSuK86nyM9ltsm9z6dcI axgpT9i8WJfFutAX+AKjcZ8AxrqImeaDpcumEe9mh6PmULMkEBuBpUBRA vdiBhHhCI23QTu1R2UZVwDhbRiVvaFtaHRfb2E7qTnfbP1zgMFqRuiS83 WJrikRC2+b22+bdkMtzdozqT5h6ltMRvRYi2fJ4EqQo74h3bTEDMbeFeY s7TmiY8n7GagpOul/roIMu+6Jv28Jc5Or+XmRXsz7YCOXuAqtUtVaPu1U Y3Cb4r4Oo0nqqEWVHj9SOCFtkufXFchRStGQzMhMiNHwEsRRpiDSYFVvN Q==; From: Vincent Whitchurch To: , , CC: , Vincent Whitchurch , , , , , , , Subject: [PATCH v2 2/2] tty: serial: samsung: Add ARTPEC-8 support Date: Fri, 11 Mar 2022 10:45:15 +0100 Message-ID: <20220311094515.3223023-3-vincent.whitchurch@axis.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220311094515.3223023-1-vincent.whitchurch@axis.com> References: <20220311094515.3223023-1-vincent.whitchurch@axis.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220311_014528_135102_0B7350E7 X-CRM114-Status: GOOD ( 16.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for the UART block on the ARTPEC-8 SoC. This is closely related to the variants used on the Exynos chips. The register layout is identical to Exynos850 et al but the fifo size is different (64 bytes in each direction for all instances). Reviewed-by: Krzysztof Kozlowski Signed-off-by: Vincent Whitchurch --- Notes: v2: - Added Krzysztof's Reviewed-by. - Expanded commit message - Fixed fifo size - Rebased on top of Krzysztof's "minor fixes/cleanups" series. This needed a couple of fixes for build errors. (I'm always unsure if Reviewed-by should be carried over or not if the fixes are minor. I apologize in advance if carring it over was the wrong thing to do in this case.) drivers/tty/serial/Kconfig | 2 +- drivers/tty/serial/samsung_tty.c | 37 ++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 0e5ccb25bdb1..bd46e35ded40 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -236,7 +236,7 @@ config SERIAL_CLPS711X_CONSOLE config SERIAL_SAMSUNG tristate "Samsung SoC serial support" - depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS || ARCH_APPLE || COMPILE_TEST + depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS || ARCH_APPLE || ARCH_ARTPEC || COMPILE_TEST select SERIAL_CORE help Support for the on-chip UARTs on the Samsung diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index 74d466cc4152..7d011d3fa3a6 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -2828,6 +2828,36 @@ static const struct s3c24xx_serial_drv_data s5l_serial_drv_data = { #define S5L_SERIAL_DRV_DATA NULL #endif +#if defined(CONFIG_ARCH_ARTPEC) +static const struct s3c24xx_serial_drv_data artpec8_serial_drv_data = { + .info = { + .name = "Axis ARTPEC-8 UART", + .type = TYPE_S3C6400, + .port_type = PORT_S3C6400, + .fifosize = 64, + .has_divslot = 1, + .rx_fifomask = S5PV210_UFSTAT_RXMASK, + .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, + .rx_fifofull = S5PV210_UFSTAT_RXFULL, + .tx_fifofull = S5PV210_UFSTAT_TXFULL, + .tx_fifomask = S5PV210_UFSTAT_TXMASK, + .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, + .def_clk_sel = S3C2410_UCON_CLKSEL0, + .num_clks = 1, + .clksel_mask = 0, + .clksel_shift = 0, + }, + .def_cfg = { + .ucon = S5PV210_UCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + .has_fracval = 1, + } +}; +#define ARTPEC8_SERIAL_DRV_DATA (&artpec8_serial_drv_data) +#else +#define ARTPEC8_SERIAL_DRV_DATA (NULL) +#endif + static const struct platform_device_id s3c24xx_serial_driver_ids[] = { { .name = "s3c2410-uart", @@ -2856,6 +2886,9 @@ static const struct platform_device_id s3c24xx_serial_driver_ids[] = { }, { .name = "exynos850-uart", .driver_data = (kernel_ulong_t)EXYNOS850_SERIAL_DRV_DATA, + }, { + .name = "artpec8-uart", + .driver_data = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA, }, { }, }; @@ -2881,6 +2914,8 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = { .data = S5L_SERIAL_DRV_DATA }, { .compatible = "samsung,exynos850-uart", .data = EXYNOS850_SERIAL_DRV_DATA }, + { .compatible = "axis,artpec8-uart", + .data = ARTPEC8_SERIAL_DRV_DATA }, {}, }; MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); @@ -3034,6 +3069,8 @@ OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart", s5pv210_early_console_setup); OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart", s5pv210_early_console_setup); +OF_EARLYCON_DECLARE(artpec8, "axis,artpec8-uart", + s5pv210_early_console_setup); /* Apple S5L */ static int __init apple_s5l_early_console_setup(struct earlycon_device *device,