From patchwork Thu Mar 17 08:22:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Irui Wang X-Patchwork-Id: 12783717 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0DC9BC433F5 for ; Thu, 17 Mar 2022 08:34:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=cjEQJxdenOrS/RV9Lf7iwGkO1giqfNW7b+JVWtX9K2M=; b=Hh1mdx6dk+c8RF LaVn48ouW3pIaAkyxQmShPApsMixLtK3/ceBsHlZ+dZJBNvuNFGNW4VkIdBLP/D5K3hud5yc2Vyny Z9swGXbsgL2AyCroHDcRRFMiHzYOmfac6HwZP3/Jbw+f5Kd/HzUIPUGNleLbFxGrvF8uDbKUe7d4P aqmidonRUZm0pMf4hggfHsBokcdoOBjNyF/4m9heCVvDFnJMfcBkmv7ZUiTcvfwn3yBrCIkZS74Y3 yne7zGgZKaf8IHtfY/gl+DCrimoz3vt16e/UkZz9yg3xxJHPMfbIoiT88qNEq5dnnwcITlWjMVIQP dCIPdr3Vvz6LVrQJ0kbw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nUlZ2-00FKed-BA; Thu, 17 Mar 2022 08:32:56 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nUlYx-00FKd0-JE; Thu, 17 Mar 2022 08:32:53 +0000 X-UUID: dd42e74ef56143fba8ce51fabb591075-20220317 X-UUID: dd42e74ef56143fba8ce51fabb591075-20220317 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1261190006; Thu, 17 Mar 2022 01:32:44 -0700 Received: from mtkmbs10n1.mediatek.inc (172.21.101.34) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 17 Mar 2022 01:23:08 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 17 Mar 2022 16:23:06 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 17 Mar 2022 16:23:04 +0800 From: Irui Wang To: Hans Verkuil , Tzung-Bi Shih , Rob Herring , Alexandre Courbot , Mauro Carvalho Chehab , Matthias Brugger , Tomasz Figa , , Yong Wu , Tiffany Lin , Andrew-CT Chen CC: Hsin-Yi Wang , Maoguang Meng , Longfei Wang , Yunfei Dong , Fritz Koenig , Irui Wang , , , , , , , Subject: [PATCH v3, 03/10] dt-bindings: media: mtk-vcodec: Adds encoder cores dt-bindings for mt8195 Date: Thu, 17 Mar 2022 16:22:23 +0800 Message-ID: <20220317082230.23622-4-irui.wang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317082230.23622-1-irui.wang@mediatek.com> References: <20220317082230.23622-1-irui.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220317_013251_657633_6A0C8A9F X-CRM114-Status: GOOD ( 16.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adds encoder cores dt-bindings for mt8195. Signed-off-by: Irui Wang --- .../media/mediatek,vcodec-encoder-core.yaml | 181 ++++++++++++++++++ .../media/mediatek,vcodec-encoder.yaml | 1 - 2 files changed, 181 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/media/mediatek,vcodec-encoder-core.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder-core.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder-core.yaml new file mode 100644 index 000000000000..fcfb48900c76 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder-core.yaml @@ -0,0 +1,181 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/media/mediatek,vcodec-encoder-core.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Mediatek Video Encoder Accelerator With Multi Core + +maintainers: + - Irui Wang + +description: | + Mediatek Video Encode is the video encode hardware present in Mediatek + SoCs which supports high resolution encoding functionalities. Required + parent and child device node. + +properties: + compatible: + items: + - enum: + - mediatek,mt8195-vcodec-enc + + mediatek,scp: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + The node of system control processor (SCP), using + the remoteproc & rpmsg framework. + + mediatek,venc-multi-core: + type: boolean + description: | + Indicates whether the encoder has multiple cores or not. + + iommus: + minItems: 1 + maxItems: 32 + description: | + List of the hardware port in respective IOMMU block for current Socs. + Refer to bindings/iommu/mediatek,iommu.yaml. + + dma-ranges: + maxItems: 1 + description: | + Describes the physical address space of IOMMU maps to memory. + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + +# Required child node: +patternProperties: + "^venc-core@[0-9a-f]+$": + type: object + description: | + The video encoder core device node which should be added as subnodes to + the main venc node. + + properties: + compatible: + items: + - const: mediatek,mtk-venc-core + + reg: + maxItems: 1 + + mediatek,core-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Current encoder core id. + + iommus: + minItems: 1 + maxItems: 32 + description: | + List of the hardware port in respective IOMMU block for current Socs. + Refer to bindings/iommu/mediatek,iommu.yaml. + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + power-domains: + maxItems: 1 + + required: + - compatible + - reg + - mediatek,core-id + - iommus + - interrupts + - clocks + - clock-names + - assigned-clocks + - assigned-clock-parents + - power-domains + + additionalProperties: false + +required: + - compatible + - mediatek,scp + - iommus + - dma-ranges + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + venc { + compatible = "mediatek,mt8195-vcodec-enc"; + mediatek,scp = <&scp>; + mediatek,venc-multi-core; + iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + + venc-core@1a020000 { + compatible = "mediatek,mtk-venc-core"; + reg = <0 0x1a020000 0 0x10000>; + mediatek,core-id = <0>; + iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, + <&iommu_vdo M4U_PORT_L19_VENC_REC>, + <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, + <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; + interrupts = ; + clocks = <&vencsys CLK_VENC_VENC>; + clock-names = "clk_venc"; + assigned-clocks = <&topckgen CLK_TOP_VENC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; + }; + + venc-core@1b020000 { + compatible = "mediatek,mtk-venc-core"; + reg = <0 0x1b020000 0 0x10000>; + mediatek,core-id = <1>; + iommus = <&iommu_vpp M4U_PORT_L20_VENC_RCPU>, + <&iommu_vpp M4U_PORT_L20_VENC_REC>, + <&iommu_vpp M4U_PORT_L20_VENC_BSDMA>, + <&iommu_vpp M4U_PORT_L20_VENC_SV_COMV>, + <&iommu_vpp M4U_PORT_L20_VENC_RD_COMV>, + <&iommu_vpp M4U_PORT_L20_VENC_CUR_LUMA>, + <&iommu_vpp M4U_PORT_L20_VENC_CUR_CHROMA>, + <&iommu_vpp M4U_PORT_L20_VENC_REF_LUMA>, + <&iommu_vpp M4U_PORT_L20_VENC_REF_CHROMA>; + interrupts = ; + clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>; + clock-names = "clk_venc_core1"; + assigned-clocks = <&topckgen CLK_TOP_VENC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml index e7b65a91c92c..0530a694bcbe 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml @@ -21,7 +21,6 @@ properties: - mediatek,mt8173-vcodec-enc - mediatek,mt8183-vcodec-enc - mediatek,mt8192-vcodec-enc - - mediatek,mt8195-vcodec-enc reg: maxItems: 1