From patchwork Thu Mar 17 16:23:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 12784290 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EBE0CC433EF for ; Thu, 17 Mar 2022 16:28:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=YdQVugWlOlHxNbP0T5MR1hvKnJ02qlj2DcnfCvRjzDw=; b=MwdXKQb3HTykJX zp6bnsqVw3Oy2fzCcEGykSW9D3E5B7qdMwXAueuesADy6pZo0dsLIMFFXwYmeRQaLPURmv4b7akNp n+eGqezMfCfxFEFYfSIVcwD4LtcAasTxTYhaERLLaxNczl56YLVi7TWNKdlpONruYI6/+fV/9GDMI ulc8/gQ5I9Ng8Vj+yIDojs1U9BxbP/3I1nNy4YDx93wO2RSzt9zVdIou7nqKkD9pFy+bND7d+zg7U d+i6JmkONMdMJtpEyF+u54zCxg6XE9/p5Vpt//fmyNifoiRhXWsJi2ySZEq26Fdbe28vScFfQIp9h RTOXgh91yQWcrHDwTOJA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nUswy-00Gl1a-A4; Thu, 17 Mar 2022 16:26:08 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nUsvG-00GkHc-09 for linux-arm-kernel@lists.infradead.org; Thu, 17 Mar 2022 16:24:23 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 35B5215DB; Thu, 17 Mar 2022 09:24:21 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.196.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3D7403F7B4; Thu, 17 Mar 2022 09:24:19 -0700 (PDT) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Rob Herring , Mesih Kilinc , Icenowy Zheng , Jesse Taube , Giulio Benetti , George Hilliard , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, Ulf Hansson , linux-mmc@vger.kernel.org Subject: [PATCH v2 08/12] ARM: dts: suniv: F1C100: add MMC controllers Date: Thu, 17 Mar 2022 16:23:45 +0000 Message-Id: <20220317162349.739636-9-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317162349.739636-1-andre.przywara@arm.com> References: <20220317162349.739636-1-andre.przywara@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220317_092422_118490_2FB4694E X-CRM114-Status: GOOD ( 10.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jesse Taube The F1C100 series contains two MMC controllers, where the first one is typically connected to an (micro)SD card slot (as this is the one the BROM is able to boot from). Describe the two controllers in the SoC .dtsi. We also add the pinctrl description for MMC0, since this is the only pin set supporting that function anyway, and SD cards are very common across boards. Signed-off-by: Jesse Taube Signed-off-by: Andre Przywara Acked-by: Samuel Holland --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 42 ++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index f455e276521e..59e0bd952f50 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -69,6 +69,42 @@ otg_sram: sram-section@0 { }; }; + mmc0: mmc@1c0f000 { + compatible = "allwinner,suniv-f1c100s-mmc", + "allwinner,sun7i-a20-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; + clock-names = "ahb", "mmc", "output", "sample"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = <23>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@1c10000 { + compatible = "allwinner,suniv-f1c100s-mmc", + "allwinner,sun7i-a20-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; + clock-names = "ahb", "mmc", "output", "sample"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = <24>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + ccu: clock@1c20000 { compatible = "allwinner,suniv-f1c100s-ccu"; reg = <0x01c20000 0x400>; @@ -96,6 +132,12 @@ pio: pinctrl@1c20800 { #interrupt-cells = <3>; #gpio-cells = <3>; + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + }; + uart0_pe_pins: uart0-pe-pins { pins = "PE0", "PE1"; function = "uart0";