@@ -20,7 +20,28 @@
DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm");
+static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)
+{
+ u32 val;
+
+ /* Set the enable bit of DSB control register to 1 */
+ val = readl_relaxed(drvdata->base + TPDM_DSB_CR);
+ val = val | BIT(0);
+ writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
+}
+
/* TPDM enable operations */
+static void _tpdm_enable(struct tpdm_drvdata *drvdata)
+{
+ CS_UNLOCK(drvdata->base);
+
+ /* Check if DSB datasets is present for TPDM. */
+ if (test_bit(TPDM_DS_DSB, drvdata->datasets))
+ tpdm_enable_dsb(drvdata);
+
+ CS_LOCK(drvdata->base);
+}
+
static int tpdm_enable(struct coresight_device *csdev,
struct perf_event *event, u32 mode)
{
@@ -32,6 +53,7 @@ static int tpdm_enable(struct coresight_device *csdev,
return -EBUSY;
}
+ _tpdm_enable(drvdata);
drvdata->enable = true;
mutex_unlock(&drvdata->lock);
@@ -39,7 +61,29 @@ static int tpdm_enable(struct coresight_device *csdev,
return 0;
}
+static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata)
+{
+ u32 val;
+
+ /* Set the enable bit of DSB control register to 0 */
+ val = readl_relaxed(drvdata->base + TPDM_DSB_CR);
+ val = val & ~BIT(0);
+ writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
+}
+
/* TPDM disable operations */
+static void _tpdm_disable(struct tpdm_drvdata *drvdata)
+{
+ CS_UNLOCK(drvdata->base);
+
+ /* Check if DSB datasets is present for TPDM. */
+ if (test_bit(TPDM_DS_DSB, drvdata->datasets))
+ tpdm_disable_dsb(drvdata);
+
+ CS_LOCK(drvdata->base);
+
+}
+
static void tpdm_disable(struct coresight_device *csdev,
struct perf_event *event)
{
@@ -51,6 +95,7 @@ static void tpdm_disable(struct coresight_device *csdev,
return;
}
+ _tpdm_disable(drvdata);
drvdata->enable = false;
mutex_unlock(&drvdata->lock);
@@ -66,6 +111,21 @@ static const struct coresight_ops tpdm_cs_ops = {
.source_ops = &tpdm_source_ops,
};
+static void tpdm_init_default_data(struct tpdm_drvdata *drvdata)
+{
+ int i;
+ u32 pidr;
+
+ CS_UNLOCK(drvdata->base);
+ /* Get the datasets present on the TPDM. */
+ pidr = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR0);
+ for (i = 0; i < TPDM_DATASETS; i++) {
+ if (pidr & BIT(i))
+ __set_bit(i, drvdata->datasets);
+ }
+ CS_LOCK(drvdata->base);
+ }
+
static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
{
struct device *dev = &adev->dev;
@@ -104,6 +164,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
if (IS_ERR(drvdata->csdev))
return PTR_ERR(drvdata->csdev);
+ tpdm_init_default_data(drvdata);
/* Decrease pm refcount when probe is done.*/
pm_runtime_put(&adev->dev);
@@ -6,6 +6,25 @@
#ifndef _CORESIGHT_CORESIGHT_TPDM_H
#define _CORESIGHT_CORESIGHT_TPDM_H
+/* The max number of the datasets that TPDM supports */
+#define TPDM_DATASETS 7
+
+/* DSB Subunit Registers */
+#define TPDM_DSB_CR (0x780)
+
+/**
+ * This enum is for PERIPHIDR0 register of TPDM.
+ * The fields [6:0] of PERIPHIDR0 are used to determine what
+ * interfaces and subunits are present on a given TPDM.
+ *
+ * PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0
+ * PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0
+ */
+enum tpdm_dataset {
+ TPDM_DS_IMPLDEF,
+ TPDM_DS_DSB,
+};
+
/**
* struct tpdm_drvdata - specifics associated to an TPDM component
* @base: memory mapped base address for this component.
@@ -13,6 +32,7 @@
* @csdev: component vitals needed by the framework.
* @lock: lock for the enable value.
* @enable: enable status of the component.
+ * @datasets: The datasets types present of the TPDM.
* @traceid: value of the current ID for this component.
*/
@@ -22,6 +42,7 @@ struct tpdm_drvdata {
struct coresight_device *csdev;
struct mutex lock;
bool enable;
+ DECLARE_BITMAP(datasets, TPDM_DATASETS);
};
#endif /* _CORESIGHT_CORESIGHT_TPDM_H */