@@ -5,6 +5,9 @@
#define kvm__arch_get_kern_offset(...) 0x8000
+struct kvm;
+static inline void kvm__arch_enable_mte(struct kvm *kvm) {}
+
#define ARM_MAX_MEMORY(...) ARM_LOMAP_MAX_MEMORY
#define MAX_PAGE_SIZE SZ_4K
@@ -6,6 +6,7 @@
struct kvm;
unsigned long long kvm__arch_get_kern_offset(struct kvm *kvm, int fd);
int kvm__arch_get_ipa_limit(struct kvm *kvm);
+void kvm__arch_enable_mte(struct kvm *kvm);
#define ARM_MAX_MEMORY(kvm) ({ \
u64 max_ram; \
@@ -6,6 +6,8 @@
"Run AArch32 guest"), \
OPT_BOOLEAN('\0', "pmu", &(cfg)->has_pmuv3, \
"Create PMUv3 device"), \
+ OPT_BOOLEAN('\0', "disable-mte", &(cfg)->mte_disabled, \
+ "Disable Memory Tagging Extension"), \
OPT_U64('\0', "kaslr-seed", &(cfg)->kaslr_seed, \
"Specify random seed for Kernel Address Space " \
"Layout Randomization (KASLR)"),
@@ -81,3 +81,25 @@ int kvm__get_vm_type(struct kvm *kvm)
return KVM_VM_TYPE_ARM_IPA_SIZE(ipa_bits);
}
+
+void kvm__arch_enable_mte(struct kvm *kvm)
+{
+ struct kvm_enable_cap cap = {
+ .cap = KVM_CAP_ARM_MTE,
+ };
+
+ if (kvm->cfg.arch.mte_disabled) {
+ pr_debug("MTE disabled by user");
+ return;
+ }
+
+ if (!kvm__supports_extension(kvm, KVM_CAP_ARM_MTE)) {
+ pr_debug("MTE capability not available");
+ return;
+ }
+
+ if (ioctl(kvm->vm_fd, KVM_ENABLE_CAP, &cap))
+ die_perror("KVM_ENABLE_CAP(KVM_CAP_ARM_MTE)");
+
+ pr_debug("MTE capability enabled");
+}
@@ -9,6 +9,7 @@ struct kvm_config_arch {
bool virtio_trans_pci;
bool aarch32_guest;
bool has_pmuv3;
+ bool mte_disabled;
u64 kaslr_seed;
enum irqchip_type irqchip;
u64 fw_addr;
@@ -86,6 +86,8 @@ void kvm__arch_init(struct kvm *kvm, const char *hugetlbfs_path, u64 ram_size)
/* Create the virtual GIC. */
if (gic__create(kvm, kvm->cfg.arch.irqchip))
die("Failed to create virtual GIC");
+
+ kvm__arch_enable_mte(kvm);
}
#define FDT_ALIGN SZ_2M