@@ -389,8 +389,23 @@ int arch_decode_instruction(struct objtool_file *file, const struct section *sec
switch (aarch64_get_insn_class(insn)) {
case AARCH64_INSN_CLS_UNKNOWN:
- WARN("can't decode instruction at %s:0x%lx", sec->name, offset);
- return -1;
+ /*
+ * There are a few reasons that non-valid opcodes in code sections:
+ * - For LDR ops, assembler can generate the data to be
+ * loaded in the code section
+ * - Compiler/assembler can generate zeroes to pad function that
+ * do not end on 8-byte alignment
+ * - Some pseudo-instructions can also generate data in code
+ * section
+ *
+ * Record these data as ignored so that they won't cause fault
+ */
+ if (insn == 0x0)
+ *type = INSN_NOP;
+ else if (record_invalid_insn(sec, offset, false))
+ return -1;
+
+ break;
case AARCH64_INSN_CLS_DP_IMM:
/* Mov register to and from SP are aliases of add_imm */
if (aarch64_insn_is_add_imm(insn) ||