From patchwork Thu Apr 7 16:23:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Elisei X-Patchwork-Id: 12805493 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0EEE3C433F5 for ; Thu, 7 Apr 2022 16:38:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Cc:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=IEeG7A8Dt6gzWghwBEY82wzpDUAFhM9O7o2Ws4w0YHo=; b=LruF7EK5DQSqrl fuZMSM31M00M9k8Q6bEQymRJReurLaEJdOdOvxhEr0MkKPLAgmToL2TPAahPQ7qDnWOn+2egBPqf0 /BbWJEPW/+kNtFC0uJ4+y9hbLjznBnqMqAajacRAgOcmjXVNfZRegMqZ5leEgv25Ksppg0XLFxe3O GAbUhw+sOpWXp0GVOHUOgPP+GgCtqY1rZpld1JYfU+yzCUDjf9X/HpsL8Q2/EFKhhxHKVAcbauctm tLaT0hsA3wrOnU7JmUfKczltl4zN9e6/iVCmN24zs9XGsiJRBSxdCWsvBLtIpLSMoDcv4i+DP1/hJ cVsMG3R+aYEOcpAT8/tQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ncV7h-00D7Gw-Es; Thu, 07 Apr 2022 16:36:41 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ncUv5-00D2QN-Vs for linux-arm-kernel@lists.infradead.org; Thu, 07 Apr 2022 16:23:45 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CE47F139F; Thu, 7 Apr 2022 09:23:35 -0700 (PDT) Received: from e121798.cable.virginm.net (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6F57D3F73B; Thu, 7 Apr 2022 09:23:34 -0700 (PDT) From: Alexandru Elisei To: catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, maz@kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, kvmarm@lists.cs.columbia.edu, mark.rutland@arm.com Subject: [PATCH 1/5] arm64: Make ESR_ELx_xVC_IMM_MASK compatible with assembly Date: Thu, 7 Apr 2022 17:23:23 +0100 Message-Id: <20220407162327.396183-2-alexandru.elisei@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220407162327.396183-1-alexandru.elisei@arm.com> References: <20220407162327.396183-1-alexandru.elisei@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220407_092340_115703_88BB0BE1 X-CRM114-Status: GOOD ( 10.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org ESR_ELx_xVC_IMM_MASK is used as a mask for the immediate value for the HVC/SMC instructions. The header file is included by assembly files (like entry.S) and ESR_ELx_xVC_IMM_MASK is not conditioned on __ASSEMBLY__ being undefined. Use the UL() macro for defining the constant's size, as that is compatible with both C code and assembly, whereas the UL suffix only works for C code. Signed-off-by: Alexandru Elisei --- arch/arm64/include/asm/esr.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h index d52a0b269ee8..7356e2f05755 100644 --- a/arch/arm64/include/asm/esr.h +++ b/arch/arm64/include/asm/esr.h @@ -136,7 +136,7 @@ #define ESR_ELx_WFx_ISS_TI (UL(1) << 0) #define ESR_ELx_WFx_ISS_WFI (UL(0) << 0) #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0) -#define ESR_ELx_xVC_IMM_MASK ((1UL << 16) - 1) +#define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1) #define DISR_EL1_IDS (UL(1) << 24) /*