From patchwork Tue Apr 12 12:50:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 12810748 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C6A96C433EF for ; Tue, 12 Apr 2022 12:55:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=cQNPLN8KVDoc/p/2q1IxQt24w4ozBnF6BhFTxYc077I=; b=QqG/k+mvsZghOm En/CRr3nsTkigl+lAwmRuJwzIl1MF2e/NtpG3yztEtq7lZ8QaFWqVEvbVImE5JHt8h6R6z7vfKKVh 6eH9Pz5xzq3YlLJgg2xYWCaqDsG4Hq61EeBC6AiYseQ7CHh3LLaGn/SSYaot5dt3eGPWvwcjQGShH RIhh/aqUq0iOijXV+2vDHBLJFAqzG2vNlhobfTxIlsR8qN/7dGgKxeEeGTq2egWuLW4KaS4ooq/zc /RfkCHYflnmh7Tcpwicigw6lk4v2/q87uDDzl343O/zUg3Tq9SFaw5eqU5UB2yebOgRVf5RU74DA1 R8bkt3d/hkFqAA0Dw8CQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1neG22-00EKdH-Ft; Tue, 12 Apr 2022 12:54:06 +0000 Received: from alexa-out.qualcomm.com ([129.46.98.28]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1neFzI-00EJYN-Kj for linux-arm-kernel@lists.infradead.org; Tue, 12 Apr 2022 12:51:18 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649767876; x=1681303876; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=H8JSIcX82wy9MO3ivpa1u0JKm3kumzErpC3StvteoSk=; b=drzFTf3q06KHVzq9q0stipoVtVf2z93z6DRnBvUID9MIk8EVWfYBRAlh kWiNDtAp9yL9LHOPpE7X1otl40KlXT2OUaWSTBPK3RK1Hs+WQuBNghxQp xqNg78q8c4ON1r1p+BS4YJZQqBVosm3immYSS6mDMkS+scY9O0WlrDGVo 8=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 12 Apr 2022 05:51:16 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2022 05:51:17 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Apr 2022 05:51:15 -0700 Received: from jinlmao-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Apr 2022 05:51:12 -0700 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin CC: Mao Jinlong , Mike Leach , Leo Yan , Greg Kroah-Hartman , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Hao Zhang , Subject: [PATCH v5 05/10] coresight-tpdm: Add integration test support Date: Tue, 12 Apr 2022 20:50:30 +0800 Message-ID: <20220412125035.40312-6-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220412125035.40312-1-quic_jinlmao@quicinc.com> References: <20220412125035.40312-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220412_055116_784922_F226A418 X-CRM114-Status: GOOD ( 20.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Integration test for tpdm can help to generate the data for verification of the topology during TPDM software bring up. Sample: echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm1/enable_source echo 1 > /sys/bus/coresight/devices/tpdm1/integration_test echo 2 > /sys/bus/coresight/devices/tpdm1/integration_test cat /dev/tmc_etf0 > /data/etf-tpdm1.bin Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong --- drivers/hwtracing/coresight/Kconfig | 9 +++ drivers/hwtracing/coresight/coresight-tpdm.c | 64 ++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 14 +++++ 3 files changed, 87 insertions(+) diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 5c506a1cd08f..60248fef4089 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -214,4 +214,13 @@ config CORESIGHT_TPDM To compile this driver as a module, choose M here: the module will be called coresight-tpdm. +config CORESIGHT_TPDM_INTEGRATION_TEST + bool "Enable CoreSight Integration Test For TPDM" + depends on CORESIGHT_TPDM + help + This option adds support for the CoreSight integration test on this + devie. Coresight architecture provides integration control modes of + operation to facilitate integration testing and software bringup + and/or to instrument topology discovery. The TPDM utilizes integration + mode to accomplish integration testing and software bringup. endif diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index d7b970cdcf51..14bccbff467d 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -126,6 +126,69 @@ static void tpdm_init_default_data(struct tpdm_drvdata *drvdata) CS_LOCK(drvdata->base); } +/* + * Define CONFIG_CORESIGHT_TPDM_INTEGRATION_TEST to enable + * integration_test sysfs nodes. It will help to generate + * tpdm data to make sure that the trace path is enabled + * and the funnel configurations are fine. + */ +#ifdef CONFIG_CORESIGHT_TPDM_INTEGRATION_TEST +/* + * value 1: 64 bits test data + * value 2: 32 bits test data + */ +static ssize_t integration_test_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + int i, ret = 0; + unsigned long val; + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + ret = kstrtoul(buf, 10, &val); + if (ret) + return ret; + + if (val != 1 && val != 2) + return -EINVAL; + + if (!drvdata->enable) + return -EINVAL; + + if (val == 1) + val = ATBCNTRL_VAL_64; + else + val = ATBCNTRL_VAL_32; + CS_UNLOCK(drvdata->base); + writel_relaxed(0x1, drvdata->base + TPDM_ITCNTRL); + + for (i = 1; i < INTEGRATION_TEST_CYCLE; i++) + writel_relaxed(val, drvdata->base + TPDM_ITATBCNTRL); + + writel_relaxed(0, drvdata->base + TPDM_ITCNTRL); + CS_LOCK(drvdata->base); + return size; +} +static DEVICE_ATTR_WO(integration_test); +#endif /* CORESIGHT_TPDM_INTEGRATION_TEST */ + +static struct attribute *tpdm_attrs[] = { +#ifdef CONFIG_CORESIGHT_TPDM_INTEGRATION_TEST + &dev_attr_integration_test.attr, +#endif /* CORESIGHT_TPDM_INTEGRATION_TEST */ + NULL, +}; + +static struct attribute_group tpdm_attr_grp = { + .attrs = tpdm_attrs, +}; + +static const struct attribute_group *tpdm_attr_grps[] = { + &tpdm_attr_grp, + NULL, +}; + static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) { struct device *dev = &adev->dev; @@ -160,6 +223,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) desc.ops = &tpdm_cs_ops; desc.pdata = adev->dev.platform_data; desc.dev = &adev->dev; + desc.groups = tpdm_attr_grps; drvdata->csdev = coresight_register(&desc); if (IS_ERR(drvdata->csdev)) return PTR_ERR(drvdata->csdev); diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 8f05070879c4..ea457ba5434e 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -12,6 +12,20 @@ /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) +/* TPDM integration test registers */ +#define TPDM_ITATBCNTRL (0xEF0) +#define TPDM_ITCNTRL (0xF00) + +/* Register value for integration test */ +#define ATBCNTRL_VAL_32 0xC00F1409 +#define ATBCNTRL_VAL_64 0xC01F1409 + +/* + * Number of cycles to write value when + * integration test. + */ +#define INTEGRATION_TEST_CYCLE 10 + /** * This enum is for PERIPHIDR0 register of TPDM. * The fields [6:0] of PERIPHIDR0 are used to determine what