| Message ID | 20220413170545.3042558-3-james.morse@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ARM/arm64: errata: Remove AES hwcap for 32bit tasks on A57/A72 | expand |
On Wed, 13 Apr 2022 at 19:06, James Morse <james.morse@arm.com> wrote: > > Cortex-A57 and Cortex-A72 have an erratum where an interrupt that > occurs between a pair of AES instructions in aarch32 mode may corrupt > the ELR. The task will subsequently produce the wrong AES result. > > The AES instructions are part of the cryptographic extensions, which are > optional. User-space software will detect the support for these > instructions from the hwcaps. If the platform doesn't support these > instructions a software implementation should be used. > > Remove the hwcap bits on affected parts to indicate user-space should > not use the AES instructions. > > Signed-off-by: James Morse <james.morse@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> > --- > arch/arm/kernel/setup.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c > index 1e8a50a97edf..8a409bfd33f2 100644 > --- a/arch/arm/kernel/setup.c > +++ b/arch/arm/kernel/setup.c > @@ -501,6 +501,15 @@ static void __init elf_hwcap_fixup(void) > return; > } > > + /* > + * HWCAP2_AES can get the wrong result due to A57's erratum #1742098 or > + * A72's #1655431. > + */ > + if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A57 || > + read_cpuid_part() == ARM_CPU_PART_CORTEX_A72) { > + elf_hwcap2 &= ~HWCAP2_AES; > + } > + > /* Verify if CPUID scheme is implemented */ > if ((id & 0x000f0000) != 0x000f0000) > return; > -- > 2.30.2 >
On Wed, Apr 13, 2022 at 06:05:45PM +0100, James Morse wrote: > Cortex-A57 and Cortex-A72 have an erratum where an interrupt that > occurs between a pair of AES instructions in aarch32 mode may corrupt > the ELR. The task will subsequently produce the wrong AES result. > > The AES instructions are part of the cryptographic extensions, which are > optional. User-space software will detect the support for these > instructions from the hwcaps. If the platform doesn't support these > instructions a software implementation should be used. > > Remove the hwcap bits on affected parts to indicate user-space should > not use the AES instructions. > > Signed-off-by: James Morse <james.morse@arm.com> Thanks James. LGTM. In time, can you drop this in the patch system please? I'm guessing we're only going to have Ard's ack on this. Thanks.
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 1e8a50a97edf..8a409bfd33f2 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -501,6 +501,15 @@ static void __init elf_hwcap_fixup(void) return; } + /* + * HWCAP2_AES can get the wrong result due to A57's erratum #1742098 or + * A72's #1655431. + */ + if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A57 || + read_cpuid_part() == ARM_CPU_PART_CORTEX_A72) { + elf_hwcap2 &= ~HWCAP2_AES; + } + /* Verify if CPUID scheme is implemented */ if ((id & 0x000f0000) != 0x000f0000) return;
Cortex-A57 and Cortex-A72 have an erratum where an interrupt that occurs between a pair of AES instructions in aarch32 mode may corrupt the ELR. The task will subsequently produce the wrong AES result. The AES instructions are part of the cryptographic extensions, which are optional. User-space software will detect the support for these instructions from the hwcaps. If the platform doesn't support these instructions a software implementation should be used. Remove the hwcap bits on affected parts to indicate user-space should not use the AES instructions. Signed-off-by: James Morse <james.morse@arm.com> --- arch/arm/kernel/setup.c | 9 +++++++++ 1 file changed, 9 insertions(+)