| Message ID | 20220414173916.5552-14-arinc.unal@arinc9.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Refactor Ralink Pinctrl and Add Documentation | expand |
On Thu, Apr 14, 2022 at 08:39:15PM +0300, Arınç ÜNAL wrote: > Add binding for the Ralink RT305X pin controller for RT3050, RT3052, > RT3350, RT3352 and RT5350 SoCs. > > Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> > --- > .../pinctrl/ralink,rt305x-pinctrl.yaml | 92 +++++++++++++++++++ > 1 file changed, 92 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml > > diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml > new file mode 100644 > index 000000000000..425401c54269 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml > @@ -0,0 +1,92 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/ralink,rt305x-pinctrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Ralink RT305X Pin Controller > + > +maintainers: > + - Arınç ÜNAL <arinc.unal@arinc9.com> > + - Sergio Paracuellos <sergio.paracuellos@gmail.com> > + > +description: > + Ralink RT305X pin controller for RT3050, RT3052, RT3350, RT3352 and RT5350 > + SoCs. > + The pin controller can only set the muxing of pin groups. Muxing individual > + pins is not supported. There is no pinconf support. > + > +properties: > + compatible: > + const: ralink,rt305x-pinctrl You should have a compatible for each SoC unless these are all just fused or package varients of the same chip. > + > +patternProperties: > + '-pins$': > + type: object > + patternProperties: > + '^(.*-)?pinmux$': > + type: object > + description: node for pinctrl. > + $ref: pinmux-node.yaml# > + > + properties: > + groups: > + description: The pin group to select. > + enum: [ > + # For RT3050, RT3052 and RT3350 SoCs > + i2c, jtag, mdio, rgmii, sdram, spi, uartf, uartlite, > + > + # For RT3352 SoC > + i2c, jtag, led, lna, mdio, pa, rgmii, spi, spi_cs1, uartf, > + uartlite, > + > + # For RT5350 SoC > + i2c, jtag, led, spi, spi_cs1, uartf, uartlite, > + ] > + > + function: > + description: The mux function to select. > + enum: [ > + # For RT3050, RT3052 and RT3350 SoCs > + gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, mdio, pcm gpio, > + pcm i2s, pcm uartf, rgmii, sdram, spi, uartf, uartlite, > + > + # For RT3352 SoC > + gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, lna, mdio, > + pa, pcm gpio, pcm i2s, pcm uartf, rgmii, spi, spi_cs1, uartf, > + uartlite, wdg_cs1, > + > + # For RT5350 SoC > + gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, pcm gpio, > + pcm i2s, pcm uartf, spi, spi_cs1, uartf, uartlite, wdg_cs1, > + ] > + > + required: > + - groups > + - function > + > + additionalProperties: false > + > + additionalProperties: false > + > +allOf: > + - $ref: "pinctrl.yaml#" > + > +required: > + - compatible > + > +additionalProperties: false > + > +examples: > + # Pinmux controller node > + - | > + pinctrl { > + compatible = "ralink,rt305x-pinctrl"; > + > + i2c_pins: i2c0-pins { > + pinmux { > + groups = "i2c"; > + function = "i2c"; > + }; > + }; > + }; > -- > 2.25.1 > >
On 19/04/2022 21:05, Rob Herring wrote: > On Thu, Apr 14, 2022 at 08:39:15PM +0300, Arınç ÜNAL wrote: >> Add binding for the Ralink RT305X pin controller for RT3050, RT3052, >> RT3350, RT3352 and RT5350 SoCs. >> >> Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> >> --- >> .../pinctrl/ralink,rt305x-pinctrl.yaml | 92 +++++++++++++++++++ >> 1 file changed, 92 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml >> >> diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml >> new file mode 100644 >> index 000000000000..425401c54269 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml >> @@ -0,0 +1,92 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pinctrl/ralink,rt305x-pinctrl.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Ralink RT305X Pin Controller >> + >> +maintainers: >> + - Arınç ÜNAL <arinc.unal@arinc9.com> >> + - Sergio Paracuellos <sergio.paracuellos@gmail.com> >> + >> +description: >> + Ralink RT305X pin controller for RT3050, RT3052, RT3350, RT3352 and RT5350 >> + SoCs. >> + The pin controller can only set the muxing of pin groups. Muxing individual >> + pins is not supported. There is no pinconf support. >> + >> +properties: >> + compatible: >> + const: ralink,rt305x-pinctrl > > You should have a compatible for each SoC unless these are all just > fused or package varients of the same chip. The rt305x pin controller calls code from arch/mips/include/asm/mach-ralink/rt305x.h to determine the SoC and uses different pinmux data by the result of the determination. I guess we can call this fused. Arınç
diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml new file mode 100644 index 000000000000..425401c54269 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ralink,rt305x-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink RT305X Pin Controller + +maintainers: + - Arınç ÜNAL <arinc.unal@arinc9.com> + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +description: + Ralink RT305X pin controller for RT3050, RT3052, RT3350, RT3352 and RT5350 + SoCs. + The pin controller can only set the muxing of pin groups. Muxing individual + pins is not supported. There is no pinconf support. + +properties: + compatible: + const: ralink,rt305x-pinctrl + +patternProperties: + '-pins$': + type: object + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + + properties: + groups: + description: The pin group to select. + enum: [ + # For RT3050, RT3052 and RT3350 SoCs + i2c, jtag, mdio, rgmii, sdram, spi, uartf, uartlite, + + # For RT3352 SoC + i2c, jtag, led, lna, mdio, pa, rgmii, spi, spi_cs1, uartf, + uartlite, + + # For RT5350 SoC + i2c, jtag, led, spi, spi_cs1, uartf, uartlite, + ] + + function: + description: The mux function to select. + enum: [ + # For RT3050, RT3052 and RT3350 SoCs + gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, mdio, pcm gpio, + pcm i2s, pcm uartf, rgmii, sdram, spi, uartf, uartlite, + + # For RT3352 SoC + gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, lna, mdio, + pa, pcm gpio, pcm i2s, pcm uartf, rgmii, spi, spi_cs1, uartf, + uartlite, wdg_cs1, + + # For RT5350 SoC + gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, pcm gpio, + pcm i2s, pcm uartf, spi, spi_cs1, uartf, uartlite, wdg_cs1, + ] + + required: + - groups + - function + + additionalProperties: false + + additionalProperties: false + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + +additionalProperties: false + +examples: + # Pinmux controller node + - | + pinctrl { + compatible = "ralink,rt305x-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + };
Add binding for the Ralink RT305X pin controller for RT3050, RT3052, RT3350, RT3352 and RT5350 SoCs. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> --- .../pinctrl/ralink,rt305x-pinctrl.yaml | 92 +++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml