| Message ID | 20220418132154.7401-2-rex-bc.chen@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Cleanup MediaTek clk reset drivers | expand |
Hi, On Mon, Apr 18, 2022 at 9:22 PM Rex-BC Chen <rex-bc.chen@mediatek.com> wrote: > The subject could be written as "Fix written reset bit offset" to make it more specific. > Original assert/deassert bit is BIT(0), but it's more resonable to modify > them to BIT(id % 32) which is based on id. > > This patch will not influence any previous driver because the reset is > only used for thermal. The id (MT8183_INFRACFG_AO_THERM_SW_RST) is 0. > > Fixes: 64ebb57a3df6 ("clk: reset: Modify reset-controller driver") > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Otherwise, Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
On Tue, 2022-04-19 at 13:48 +0800, Chen-Yu Tsai wrote: > Hi, > > On Mon, Apr 18, 2022 at 9:22 PM Rex-BC Chen <rex-bc.chen@mediatek.com > > wrote: > > > > The subject could be written as "Fix written reset bit offset" to > make it > more specific. Hello ChenYu, I will update the topic in next version. Thanks for your suggestion. BRs, Rex > > > Original assert/deassert bit is BIT(0), but it's more resonable to > > modify > > them to BIT(id % 32) which is based on id. > > > > This patch will not influence any previous driver because the reset > > is > > only used for thermal. The id (MT8183_INFRACFG_AO_THERM_SW_RST) is > > 0. > > > > Fixes: 64ebb57a3df6 ("clk: reset: Modify reset-controller driver") > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> > > Otherwise, > > Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index bcec4b89f449..834d26e9bdfd 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -25,7 +25,7 @@ static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev, struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); unsigned int reg = data->regofs + ((id / 32) << 4); - return regmap_write(data->regmap, reg, 1); + return regmap_write(data->regmap, reg, BIT(id % 32)); } static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev, @@ -34,7 +34,7 @@ static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev, struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); unsigned int reg = data->regofs + ((id / 32) << 4) + 0x4; - return regmap_write(data->regmap, reg, 1); + return regmap_write(data->regmap, reg, BIT(id % 32)); } static int mtk_reset_assert(struct reset_controller_dev *rcdev,
Original assert/deassert bit is BIT(0), but it's more resonable to modify them to BIT(id % 32) which is based on id. This patch will not influence any previous driver because the reset is only used for thermal. The id (MT8183_INFRACFG_AO_THERM_SW_RST) is 0. Fixes: 64ebb57a3df6 ("clk: reset: Modify reset-controller driver") Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> --- drivers/clk/mediatek/reset.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)