From patchwork Tue Apr 19 06:55:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817501 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9B304C433EF for ; Tue, 19 Apr 2022 07:02:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=23BSVB8OTl209XVL6WJW0UpR11ei42jQAel9XPk3fPs=; b=ytc0g8+vbUcHBq/VeUz1Zt7x2m JjT1l5gC5uMfabUY3QXowiH9OU+QNyQOAh9c3PM3aHoG64AoVROaaSAEPX1OltPzNoIuSEJZnosra grk7CWg5BeReNeDyKWHvqCtYjdwYZoZEw++vMqFW0MZifp3TRbYKWTnibNAMY9gPtrK0l0Ms4qEuy uaavLuHM9F1QOjVMfkoQTUYpkHrq1TJTu0Dc/tg9SfShRsWeHxEUPMs4L7SavDybivlKJfNkEfA7t 274tmtsAayDxH5nXHiTyPXfnVW361tdtMqZzPLO1sDXLUfiBNDMP9VKdpv2tOYAszY6U4h4gBT6hI nZ9ZMyDg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghrm-001pCA-D2; Tue, 19 Apr 2022 07:01:39 +0000 Received: from mail-pj1-x104a.google.com ([2607:f8b0:4864:20::104a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghng-001nSR-Ol for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:26 +0000 Received: by mail-pj1-x104a.google.com with SMTP id m8-20020a17090aab0800b001cb1320ef6eso1184668pjq.3 for ; Mon, 18 Apr 2022 23:57:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=5GFeg0Qhkqt0F/Jtoeb93WWvQllcpb+IlKZnd70ZJik=; b=Fv4yxIMKsOfPGl1VWc42zdtocbfbfZISNCLx3NGwULK0h1JKlUIWpfnlR/UL/RRMyA eKMYR3vCEvPzuoFW6dKiSVM7mNuCTj58732pG3PZ8cRx/V/jpgNu+AzLyMznTWkU7AYm XEbug58FYBe7rIGRKQkJPaCRjF6EBPjlknVNwBqVFn/SJT1P9Opmpy/2CQpay9I+WDBe hZwitU1DkclcjVe3OR1Fg1KMkZ5GPGfwYoC4VNzLLHXq+DhNlaG572W/i2tRZU+M/i+i Wp5xaAMVEBc0q1E5xZnp3K5MrJ62+uiDQ2cSm3mL+VFCJUUn4k8M7XbGWaLgDE7OWKPp ttBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=5GFeg0Qhkqt0F/Jtoeb93WWvQllcpb+IlKZnd70ZJik=; b=EnbVqtFWVer+Gqv36QEMCb3D/c1zORW2lQjmjOGtjJRxWpxNFzQ7XGhO54rdR8OIcy w93RfSG2cZCfeao2vYoSsOa0vITuqmN4N74tXPDAHEkUacz8P05fX9OtRpeekC9PAJvM uAFBadMY+6OCsGUxmgIig77B60M2cGT47sLCJSOPsxDNNpn9uaCukde3ovS3/KiLHstT 73aS14a/pqvx+pWqrc69ostO3lqR7UO9nzKFf3yfcxFzpOuAlnzre/zGbPgA8PLjBcA7 NMjOHHK9w/fk9K08JDex3GpQPYYrWsKSVAyBcS3nkcBslr7wNBGvTBre1j1e408y6hWu QSVA== X-Gm-Message-State: AOAM533mXox5rCifXn9cdScEacziU5lJaJIj0Io5J92KhVznJjON9903 AMbUnlLWU7g9cn1JYntXj0rKthJniIE= X-Google-Smtp-Source: ABdhPJxWTrb+BY8xwpwyXUFdaoymj4StHXGAR+lBoWQZOnAwK6U8eNBK6/ve0byeXMAGA0OzQxHDtDdAAhc= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a17:902:9696:b0:158:f809:310e with SMTP id n22-20020a170902969600b00158f809310emr9827150plp.16.1650351443506; Mon, 18 Apr 2022 23:57:23 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:17 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-12-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 11/38] KVM: arm64: Make ID_AA64MMFR0_EL1 writable From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235724_846166_8D5828D7 X-CRM114-Status: GOOD ( 21.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds id_reg_desc for ID_AA64MMFR0_EL1 to make it writable by userspace. Since ID_AA64MMFR0_EL1 stage 2 granule size fields don't follow the standard ID scheme, we need a special handling to validate those fields. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/sys_regs.c | 133 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index ba2e6dac7774..b68ae53af792 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -542,6 +542,118 @@ static int validate_id_aa64isar2_el1(struct kvm_vcpu *vcpu, return 0; } +/* + * Check if the requested stage2 translation granule size indicated in + * @mmfr0 is also indicated in @mmfr0_lim. + * If TGranX_2 field is zero, the value must be validated based on TGranX + * field because that indicates the feature support is identified in + * TGranX field. + * This function relies on the fact TGranX fields are validated before + * through arm64_check_features. + */ +static int aa64mmfr0_tgran2_check(int field, u64 mmfr0, u64 mmfr0_lim) +{ + s64 tgran2, lim_tgran2, rtgran1; + int f1; + bool is_signed; + + tgran2 = cpuid_feature_extract_unsigned_field(mmfr0, field); + lim_tgran2 = cpuid_feature_extract_unsigned_field(mmfr0_lim, field); + if (tgran2 && lim_tgran2) + /* + * We don't need to check TGranX field. We can simply + * compare tgran2 and lim_tgran2. + */ + return (tgran2 > lim_tgran2) ? -E2BIG : 0; + + if (tgran2 == lim_tgran2) + /* + * Both of them are zero. Since TGranX in @mmfr0 is already + * validated by arm64_check_features, tgran2 must be fine. + */ + return 0; + + /* + * Either tgran2 or lim_tgran2 is zero. + * Need stage1 granule size to validate tgran2. + */ + + /* + * Get TGranX's bit position by subtracting 12 from TGranX_2's bit + * position. + */ + f1 = field - 12; + + /* TGran4/TGran64 is signed and TGran16 is unsigned field. */ + is_signed = (f1 == ID_AA64MMFR0_TGRAN16_SHIFT) ? false : true; + + /* + * If tgran2 == 0 (&& lim_tgran2 != 0), the requested stage2 granule + * size is indicated in the stage1 granule size field of @mmfr0. + * So, validate the stage1 granule size against the stage2 limit + * granule size. + * If lim_tgran2 == 0 (&& tgran2 != 0), the stage2 limit granule size + * is indicated in the stage1 granule size field of @mmfr0_lim. + * So, validate the requested stage2 granule size against the stage1 + * limit granule size. + */ + + /* Get the relevant stage1 granule size to validate tgran2 */ + if (tgran2 == 0) + /* The requested stage1 granule size */ + rtgran1 = cpuid_feature_extract_field(mmfr0, f1, is_signed); + else /* lim_tgran2 == 0 */ + /* The stage1 limit granule size */ + rtgran1 = cpuid_feature_extract_field(mmfr0_lim, f1, is_signed); + + /* + * Adjust the value of rtgran1 to compare with stage2 granule size, + * which indicates: 1: Not supported, 2: Supported, etc. + */ + if (is_signed) + /* For signed, -1: Not supported, 0: Supported, etc. */ + rtgran1 += 0x2; + else + /* For unsigned, 0: Not supported, 1: Supported, etc. */ + rtgran1 += 0x1; + + if ((tgran2 == 0) && (rtgran1 > lim_tgran2)) + /* + * The requested stage1 granule size (== the requested stage2 + * granule size) is larger than the stage2 limit granule size. + */ + return -E2BIG; + else if ((lim_tgran2 == 0) && (tgran2 > rtgran1)) + /* + * The requested stage2 granule size is larger than the stage1 + * limit granulze size (== the stage2 limit granule size). + */ + return -E2BIG; + + return 0; +} + +static int validate_id_aa64mmfr0_el1(struct kvm_vcpu *vcpu, + const struct id_reg_desc *id_reg, u64 val) +{ + u64 limit = id_reg->vcpu_limit_val; + int ret; + + ret = aa64mmfr0_tgran2_check(ID_AA64MMFR0_TGRAN4_2_SHIFT, val, limit); + if (ret) + return ret; + + ret = aa64mmfr0_tgran2_check(ID_AA64MMFR0_TGRAN64_2_SHIFT, val, limit); + if (ret) + return ret; + + ret = aa64mmfr0_tgran2_check(ID_AA64MMFR0_TGRAN16_2_SHIFT, val, limit); + if (ret) + return ret; + + return 0; +} + static void init_id_aa64pfr0_el1_desc(struct id_reg_desc *id_reg) { u64 limit = id_reg->vcpu_limit_val; @@ -3413,6 +3525,24 @@ static struct id_reg_desc id_aa64isar2_el1_desc = { }, }; +static struct id_reg_desc id_aa64mmfr0_el1_desc = { + .reg_desc = ID_SANITISED(ID_AA64MMFR0_EL1), + /* + * When TGranX_2 value is 0, validity of the value depend on TGranX + * value, and TGranX_2 value must be validated against TGranX value, + * which is done by validate_id_aa64mmfr0_el1. + * So, skip the regular validity checking for TGranX_2 fields. + */ + .ignore_mask = ARM64_FEATURE_MASK(ID_AA64MMFR0_TGRAN4_2) | + ARM64_FEATURE_MASK(ID_AA64MMFR0_TGRAN64_2) | + ARM64_FEATURE_MASK(ID_AA64MMFR0_TGRAN16_2), + .validate = validate_id_aa64mmfr0_el1, + .ftr_bits = { + S_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, ID_AA64MMFR0_TGRAN64_NI), + S_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, ID_AA64MMFR0_TGRAN4_NI), + }, +}; + #define ID_DESC(id_reg_name, id_reg_desc) \ [IDREG_IDX(SYS_##id_reg_name)] = (id_reg_desc) @@ -3426,6 +3556,9 @@ static struct id_reg_desc *id_reg_desc_table[KVM_ARM_ID_REG_MAX_NUM] = { ID_DESC(ID_AA64ISAR0_EL1, &id_aa64isar0_el1_desc), ID_DESC(ID_AA64ISAR1_EL1, &id_aa64isar1_el1_desc), ID_DESC(ID_AA64ISAR2_EL1, &id_aa64isar2_el1_desc), + + /* CRm=7 */ + ID_DESC(ID_AA64MMFR0_EL1, &id_aa64mmfr0_el1_desc), }; static inline struct id_reg_desc *get_id_reg_desc(u32 id)