[V2,1/2] EDAC: synopsys: Add disable_intr support for V3.X Synopsys EDAC DDR

Commit Message

Sherry Sun April 21, 2022, 1:53 a.m. UTC

V3.X Synopsys EDAC DDR doesn't have the QOS Interrupt register, need
to change to use the ECC Clear Register to disable the interrupts.

Signed-off-by: Sherry Sun <[e-mail]>
Reviewed-by: Shubhrajyoti Datta <[e-mail]>
Acked-by: Michal Simek <[e-mail]>
---
Changes in V2:
1. Add the Reviewed-by and Acked-by tag.
---
 drivers/edac/synopsys_edac.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

Comments

Borislav Petkov April 21, 2022, 8:58 a.m. UTC | #1

> Subject: Re: [PATCH V2 1/2] EDAC: synopsys: Add disable_intr support for V3.X Synopsys EDAC DDR

EDAC tree subject prefixes are of the format:

EDAC/<driver name>: Bla...

where "Bla starts with a capital letter".

What is "disable_intr support"?

I can figure it out when looking at the code but you need to make this
human-readable. For example

"Disable the error interrupt on Synopsys EDAC v3.x hardware"

Also, is it all caps V3.X or is it simply v3.x?

On Thu, Apr 21, 2022 at 09:53:12AM +0800, Sherry Sun wrote:
> V3.X Synopsys EDAC DDR doesn't have the QOS Interrupt register, need
> to change to use the ECC Clear Register to disable the interrupts.

Not "need to change" but "change".

From Documentation/process/submitting-patches.rst:

"Describe your changes in imperative mood, e.g. "make xyzzy do frotz"
instead of "[This patch] makes xyzzy do frotz" or "[I] changed xyzzy
to do frotz", as if you are giving orders to the codebase to change
its behaviour."

Please have a look at that document.

Thx.

Patch

diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
index 40b1abeca856..88a481043d4c 100644
--- a/drivers/edac/synopsys_edac.c
+++ b/drivers/edac/synopsys_edac.c
@@ -865,8 +865,11 @@  static void enable_intr(struct synps_edac_priv *priv)
 static void disable_intr(struct synps_edac_priv *priv)
 {
 	/* Disable UE/CE Interrupts */
-	writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
-			priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
+	if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
+		writel(0x0, priv->baseaddr + ECC_CLR_OFST);
+	else
+		writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
+		       priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
 }
 
 static int setup_irq(struct mem_ctl_info *mci,